SRAM_CTRL/MAIN Simulation Results

Tuesday April 22 2025 18:31:12 UTC

GitHub Revision: ebd55f1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	5.430s	1.401ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.630s	14.822us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.740s	14.973us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.270s	96.503us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.490s	59.961us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.360s	366.355us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.740s	14.973us	1	1	100.00
		sram_ctrl_csr_aliasing	1.490s	59.961us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.736m	5.257ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.492m	1.661ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	3.833m	10.163ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	1.420m	2.948ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	19.995m	52.028ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	7.629m	12.563ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.024m	28.912ms	1	1	100.00
V2	executable	sram_ctrl_executable	11.691m	30.750ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	18.090s	3.434ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.970m	17.882ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	26.620s	3.341ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	27.600s	753.247us	1	1	100.00
		sram_ctrl_throughput_w_readback	17.320s	814.383us	1	1	100.00
V2	regwen	sram_ctrl_regwen	5.455m	2.281ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.270s	802.689us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	58.616m	96.205ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.860s	13.425us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.040s	64.026us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.040s	64.026us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.630s	14.822us	1	1	100.00
		sram_ctrl_csr_rw	1.740s	14.973us	1	1	100.00
		sram_ctrl_csr_aliasing	1.490s	59.961us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.710s	130.378us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.630s	14.822us	1	1	100.00
		sram_ctrl_csr_rw	1.740s	14.973us	1	1	100.00
		sram_ctrl_csr_aliasing	1.490s	59.961us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.710s	130.378us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	19.590s	15.361ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.570s	8.183us	0	1	0.00
		sram_ctrl_tl_intg_err	2.400s	102.542us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.570s	8.183us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.400s	102.542us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	5.455m	2.281ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	5.455m	2.281ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.740s	14.973us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	11.691m	30.750ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	11.691m	30.750ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	11.691m	30.750ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.024m	28.912ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	5.070s	3.908ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	19.590s	15.361ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.720s	688.856us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	5.430s	1.401ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	5.430s	1.401ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	11.691m	30.750ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.570s	8.183us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.024m	28.912ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.570s	8.183us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.570s	8.183us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	5.430s	1.401ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.570s	8.183us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	12.780s	2.353ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(!$isunknown(rdata_o))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.60004267264530306932491491867880750010795409570122028486324019136602511007207
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   8183421 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   8183421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---