SRAM_CTRL/RET Simulation Results

Tuesday April 22 2025 18:31:12 UTC

GitHub Revision: ebd55f1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	9.780s	199.988us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.550s	16.235us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.000s	17.055us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.330s	401.901us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.640s	48.371us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.670s	382.686us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.000s	17.055us	1	1	100.00
		sram_ctrl_csr_aliasing	1.640s	48.371us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.640s	144.685us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	4.920s	1.268ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	8.873m	15.389ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.053m	3.572ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	24.060s	5.754ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	1.886m	929.844us	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	7.060s	5.231ms	1	1	100.00
V2	executable	sram_ctrl_executable	4.721m	26.162ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	47.210s	2.073ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.375m	4.927ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	50.840s	650.903us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	2.550s	116.566us	1	1	100.00
		sram_ctrl_throughput_w_readback	26.090s	442.568us	1	1	100.00
V2	regwen	sram_ctrl_regwen	10.581m	6.959ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.510s	47.689us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	23.733m	29.198ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.700s	28.807us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.310s	71.844us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.310s	71.844us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.550s	16.235us	1	1	100.00
		sram_ctrl_csr_rw	2.000s	17.055us	1	1	100.00
		sram_ctrl_csr_aliasing	1.640s	48.371us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.640s	32.596us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.550s	16.235us	1	1	100.00
		sram_ctrl_csr_rw	2.000s	17.055us	1	1	100.00
		sram_ctrl_csr_aliasing	1.640s	48.371us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.640s	32.596us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.850s	1.138ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.810s	9.376us	0	1	0.00
		sram_ctrl_tl_intg_err	2.800s	519.949us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.810s	9.376us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.800s	519.949us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	10.581m	6.959ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	10.581m	6.959ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.000s	17.055us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	4.721m	26.162ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	4.721m	26.162ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	4.721m	26.162ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	7.060s	5.231ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.870s	134.836us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.850s	1.138ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.780s	449.443us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	9.780s	199.988us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	9.780s	199.988us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	4.721m	26.162ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.810s	9.376us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	7.060s	5.231ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.810s	9.376us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.810s	9.376us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	9.780s	199.988us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.810s	9.376us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	56.310s	376.518us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.83869432697361538451980420411429147303679352593085173736448570090063851807913
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 449443055 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x29) != exp (0x60)
        UVM_INFO @ 449443055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.1558273561471463184737059965960502064484116558200909232143159397970677385737
      Line 98, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   9376195 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   9376195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---