SYSRST_CTRL Simulation Results

Tuesday April 22 2025 18:31:12 UTC

GitHub Revision: ebd55f1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 2.550s 2.124ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 3.290s 2.459ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 3.870s 2.443ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 5.490s 2.254ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 8.790s 4.014ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 3.020s 2.059ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 10.050s 3.106ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 3.450s 2.577ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 2.870s 2.098ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 3.020s 2.059ms 1 1 100.00
sysrst_ctrl_csr_aliasing 3.450s 2.577ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 24.960s 23.849ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 48.560s 98.044ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 7.990s 3.188ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 2.000s 3.125ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 7.080s 2.511ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 2.060s 2.288ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 4.710s 2.929ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 6.870s 2.609ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 3.380s 3.874ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 19.640s 38.588ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 1.330m 166.080ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 2.470s 2.031ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 6.430s 2.015ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 3.610s 2.164ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 3.610s 2.164ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 8.790s 4.014ms 1 1 100.00
sysrst_ctrl_csr_rw 3.020s 2.059ms 1 1 100.00
sysrst_ctrl_csr_aliasing 3.450s 2.577ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 9.460s 7.025ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 8.790s 4.014ms 1 1 100.00
sysrst_ctrl_csr_rw 3.020s 2.059ms 1 1 100.00
sysrst_ctrl_csr_aliasing 3.450s 2.577ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 9.460s 7.025ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 51.970s 42.036ms 1 1 100.00
sysrst_ctrl_tl_intg_err 40.390s 42.541ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 40.390s 42.541ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 6.560s 6.969ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00