UART Simulation Results

Tuesday April 22 2025 18:31:12 UTC

GitHub Revision: ebd55f1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	16.470s	6.270ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.650s	1.066ms	1	1	100.00
V1	csr_rw	uart_csr_rw	1.470s	35.322us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.050s	35.682us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.980s	162.294us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.460s	74.240us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.470s	35.322us	1	1	100.00
		uart_csr_aliasing	1.980s	162.294us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	43.730s	142.196ms	1	1	100.00
V2	parity	uart_smoke	16.470s	6.270ms	1	1	100.00
		uart_tx_rx	43.730s	142.196ms	1	1	100.00
V2	parity_error	uart_intr	12.050s	27.700ms	1	1	100.00
		uart_rx_parity_err	1.199m	117.803ms	1	1	100.00
V2	watermark	uart_tx_rx	43.730s	142.196ms	1	1	100.00
		uart_intr	12.050s	27.700ms	1	1	100.00
V2	fifo_full	uart_fifo_full	1.719m	97.147ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	21.320s	78.160ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	9.190s	7.588ms	1	1	100.00
V2	rx_frame_err	uart_intr	12.050s	27.700ms	1	1	100.00
V2	rx_break_err	uart_intr	12.050s	27.700ms	1	1	100.00
V2	rx_timeout	uart_intr	12.050s	27.700ms	1	1	100.00
V2	perf	uart_perf	8.634m	13.182ms	1	1	100.00
V2	sys_loopback	uart_loopback	3.440s	9.205ms	1	1	100.00
V2	line_loopback	uart_loopback	3.440s	9.205ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	12.060s	19.454ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	20.190s	36.457ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	4.070s	1.186ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	31.590s	5.223ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	3.315m	86.177ms	1	1	100.00
V2	stress_all	uart_stress_all	10.377m	158.983ms	1	1	100.00
V2	alert_test	uart_alert_test	1.450s	74.755us	1	1	100.00
V2	intr_test	uart_intr_test	1.450s	40.714us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.280s	128.072us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.280s	128.072us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.650s	1.066ms	1	1	100.00
		uart_csr_rw	1.470s	35.322us	1	1	100.00
		uart_csr_aliasing	1.980s	162.294us	1	1	100.00
		uart_same_csr_outstanding	1.750s	32.243us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.650s	1.066ms	1	1	100.00
		uart_csr_rw	1.470s	35.322us	1	1	100.00
		uart_csr_aliasing	1.980s	162.294us	1	1	100.00
		uart_same_csr_outstanding	1.750s	32.243us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.730s	71.762us	1	1	100.00
		uart_tl_intg_err	1.610s	190.049us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.610s	190.049us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	27.760s	28.144ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00