CHIP Simulation Results

Tuesday April 22 2025 18:31:12 UTC

GitHub Revision: `ebd55f1`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.861m	3.142ms	1	1	100.00
		chip_sw_example_rom	1.387m	2.355ms	1	1	100.00
		chip_sw_example_manufacturer	1.986m	2.982ms	1	1	100.00
		chip_sw_example_concurrency	2.306m	2.653ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.572m	4.469ms	1	1	100.00
V1	csr_rw	chip_csr_rw	2.955m	4.281ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	3.440m	4.494ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	58.357m	32.383ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	49.470s	2.862ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	58.357m	32.383ms	1	1	100.00
		chip_csr_rw	2.955m	4.281ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	5.620s	156.395us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.103m	4.682ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.103m	4.682ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.103m	4.682ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.068m	4.059ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.068m	4.059ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	6.038m	4.380ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.327m	3.993ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.715m	3.766ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	4.623m	4.153ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	4.683m	3.924ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	3.740m	3.750ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.531m	5.170ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.531m	5.170ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.357m	3.598ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.608m	3.291ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.065m	3.190ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	1.424m	2.921ms	1	1	100.00
		chip_tap_straps_testunlock0	2.226m	3.131ms	1	1	100.00
		chip_tap_straps_rma	2.821m	4.074ms	1	1	100.00
		chip_tap_straps_prod	1.608m	2.660ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.164m	2.598ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	10.759m	8.458ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.232m	4.909ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.232m	4.909ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	10.784m	7.801ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	19.273m	16.344ms	1	1	100.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.307m	3.815ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.096m	5.842ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.466m	19.014ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.115m	2.687ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.552m	6.063ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.705m	3.192ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	14.364m	8.266ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.152m	2.827ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.677m	5.008ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.683m	3.051ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.939m	3.372ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	10.092m	8.723ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.389m	4.971ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.363m	2.674ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.389m	4.971ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.396m	2.839ms	1	1	100.00
		chip_sw_aes_smoketest	2.767m	3.430ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.704m	2.797ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.928m	2.907ms	1	1	100.00
		chip_sw_csrng_smoketest	1.750m	2.283ms	1	1	100.00
		chip_sw_entropy_src_smoketest	3.727m	3.485ms	1	1	100.00
		chip_sw_gpio_smoketest	2.335m	2.943ms	1	1	100.00
		chip_sw_hmac_smoketest	3.620m	3.522ms	1	1	100.00
		chip_sw_kmac_smoketest	2.393m	2.588ms	1	1	100.00
		chip_sw_otbn_smoketest	9.464m	5.746ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.125m	6.143ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.321m	6.572ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.014m	3.032ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.636m	2.910ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.587m	2.038ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.855m	2.972ms	1	1	100.00
		chip_sw_uart_smoketest	2.538m	2.598ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	1.954m	2.972ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	5.149m	5.128ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.974h	60.685ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	37.554m	14.745ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.514m	4.908ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.697m	3.735ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	3.224m	3.249ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.883h	53.102ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.787h	57.075ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	54.680s	2.571ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	54.680s	2.571ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	58.357m	32.383ms	1	1	100.00
		chip_same_csr_outstanding	38.996m	29.120ms	1	1	100.00
		chip_csr_hw_reset	2.572m	4.469ms	1	1	100.00
		chip_csr_rw	2.955m	4.281ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	58.357m	32.383ms	1	1	100.00
		chip_same_csr_outstanding	38.996m	29.120ms	1	1	100.00
		chip_csr_hw_reset	2.572m	4.469ms	1	1	100.00
		chip_csr_rw	2.955m	4.281ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	24.830s	502.591us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.800s	44.391us	1	1	100.00
		xbar_smoke_large_delays	1.054m	10.292ms	1	1	100.00
		xbar_smoke_slow_rsp	52.900s	6.196ms	1	1	100.00
		xbar_random_zero_delays	6.400s	65.417us	1	1	100.00
		xbar_random_large_delays	4.919m	50.942ms	1	1	100.00
		xbar_random_slow_rsp	2.480m	17.092ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	27.550s	1.068ms	1	1	100.00
		xbar_error_and_unmapped_addr	15.110s	573.585us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	15.550s	773.853us	1	1	100.00
		xbar_error_and_unmapped_addr	15.110s	573.585us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	16.380s	304.963us	1	1	100.00
		xbar_access_same_device_slow_rsp	7.155m	51.187ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	33.420s	1.520ms	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	35.110s	1.482ms	1	1	100.00
		xbar_stress_all_with_error	1.169m	1.756ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	2.060m	1.035ms	1	1	100.00
		xbar_stress_all_with_reset_error	1.092m	444.004us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	37.554m	14.745ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	33.625m	27.207ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	39.076m	14.793ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	32.662m	11.168ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	40.606m	15.464ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	39.037m	15.491ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	41.397m	15.585ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	38.730m	14.904ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	28.300s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	30.510s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	27.370s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	27.390s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	27.560s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	26.550s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	26.570s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	26.600s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	28.890s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	27.940s	10.400us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	26.370s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	26.560s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	26.220s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	25.570s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	27.430s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	25.490s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	26.460s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	26.120s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	24.870s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	25.120s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	25.380s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	27.590s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	27.740s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	25.780s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	27.980s	10.140us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	29.653m	11.004ms	1	1	100.00
		rom_e2e_asm_init_dev	37.230m	14.994ms	1	1	100.00
		rom_e2e_asm_init_prod	37.471m	15.414ms	1	1	100.00
		rom_e2e_asm_init_prod_end	37.382m	15.683ms	1	1	100.00
		rom_e2e_asm_init_rma	36.504m	14.489ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	37.513m	14.654ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	35.833m	14.248ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	37.187m	14.677ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	36.252m	15.333ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	6.142m	18.610ms	1	1	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	6.142m	18.610ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	3.014m	3.161ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.115m	2.687ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.429m	2.981ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.732m	2.969ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	19.266m	10.158ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.900m	3.300ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	5.728m	6.194ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	2.869m	3.421ms	0	1	0.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	10.017m	5.400ms	1	1	100.00
		chip_plic_all_irqs_10	4.387m	4.190ms	1	1	100.00
		chip_plic_all_irqs_20	6.048m	4.517ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	3.150m	3.497ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	13.962m	13.607ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.654m	3.511ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.480m	2.729ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	10.052m	11.270ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	19.261m	8.966ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	11.974m	6.586ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	13.501m	8.336ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	1.987h	255.694ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	4.581m	4.072ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.125m	6.143ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	4.581m	4.072ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.451m	8.112ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.451m	8.112ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.260m	8.231ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	5.814m	5.652ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	8.454m	5.920ms	1	1	100.00
		chip_sw_aes_idle	2.732m	2.969ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.998m	3.459ms	1	1	100.00
		chip_sw_kmac_idle	1.867m	3.043ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	2.932m	3.905ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	3.124m	4.255ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.123m	4.270ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.580m	4.789ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	10.534m	10.412ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.350m	3.793ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.078m	4.906ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.926m	4.097ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.422m	4.638ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.925m	4.360ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.585m	4.092ms	1	1	100.00
		chip_sw_ast_clk_outputs	10.784m	7.801ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	4.089m	7.409ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.926m	4.097ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.422m	4.638ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.307m	3.815ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.096m	5.842ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.466m	19.014ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.115m	2.687ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.552m	6.063ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.705m	3.192ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	14.364m	8.266ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.152m	2.827ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.677m	5.008ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.683m	3.051ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.233m	3.103ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.649m	4.375ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.332m	7.328ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	49.947m	25.228ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.121m	3.048ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.535m	2.886ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	13.789m	9.958ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.890m	2.677ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.281m	4.680ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	16.842m	24.143ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	44.163m	26.302ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	10.784m	7.801ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.732m	4.902ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	4.074m	4.054ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	2.869m	3.421ms	0	1	0.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	19.261m	8.966ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	13.696m	6.570ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.927m	2.766ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.841m	6.509ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.845m	2.839ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.219h	28.736ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.067m	2.268ms	1	1	100.00
		chip_sw_edn_entropy_reqs	10.911m	6.738ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.067m	2.268ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	13.696m	6.570ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.675m	2.861ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	20.354m	24.302ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	8.720m	4.686ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.096m	5.842ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.341m	4.313ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.307m	3.815ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	55.777m	43.684ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	20.354m	24.302ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.542m	3.835ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	16.331m	9.080ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.274m	5.801ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	55.777m	43.684ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.274m	5.801ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.274m	5.801ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	5.274m	5.801ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.274m	5.801ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	2.869m	3.421ms	0	1	0.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	1.611m	5.201ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	7.828m	4.984ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.975m	5.461ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.975m	5.461ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.880m	2.427ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.705m	3.192ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.998m	3.459ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	3.418m	3.548ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	13.851m	7.443ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.679m	4.646ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.849m	4.759ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	6.908m	4.970ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.085m	3.989ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	16.331m	9.080ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	14.364m	8.266ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	21.657m	11.012ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	19.266m	10.158ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	40.777m	13.250ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.220m	2.631ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.593m	2.955ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.152m	2.827ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	16.331m	9.080ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	8.286m	10.001ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.700m	3.110ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	16.487m	8.066ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	1.867m	3.043ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	5.728m	6.194ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	1.424m	2.921ms	1	1	100.00
		chip_tap_straps_rma	2.821m	4.074ms	1	1	100.00
		chip_tap_straps_prod	1.608m	2.660ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.544m	2.830ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	8.286m	10.001ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	8.286m	10.001ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	8.286m	10.001ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	22.728m	11.786ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	5.274m	5.801ms	1	1	100.00
		chip_sw_flash_rma_unlocked	55.777m	43.684ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.152m	2.681ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.929m	7.269ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.433m	6.418ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.921m	7.742ms	1	1	100.00
		chip_sw_lc_ctrl_transition	8.286m	10.001ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.331m	9.080ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	4.978m	9.147ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	8.474m	8.483ms	1	1	100.00
		chip_prim_tl_access	1.611m	5.201ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	4.089m	7.409ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.350m	3.793ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.078m	4.906ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.926m	4.097ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.422m	4.638ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.925m	4.360ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.585m	4.092ms	1	1	100.00
		chip_tap_straps_dev	1.424m	2.921ms	1	1	100.00
		chip_tap_straps_rma	2.821m	4.074ms	1	1	100.00
		chip_tap_straps_prod	1.608m	2.660ms	1	1	100.00
		chip_rv_dm_lc_disabled	7.950m	26.891ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.793m	2.702ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.707m	3.531ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.670m	3.582ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.361m	3.471ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	20.013m	25.675ms	1	1	100.00
		chip_rv_dm_lc_disabled	7.950m	26.891ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	56.538m	49.688ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.055h	46.745ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	7.143m	8.235ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	59.806m	46.895ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	20.013m	25.675ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.102m	1.763ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.170m	2.573ms	1	1	100.00
		rom_volatile_raw_unlock	1.245m	3.194ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	55.602m	17.640ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.466m	19.014ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	8.454m	5.920ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	8.454m	5.920ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	8.454m	5.920ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.425m	3.990ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	8.286m	10.001ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	20.354m	24.302ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.425m	3.990ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.331m	9.080ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.903m	4.660ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.852m	3.098ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	20.354m	24.302ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.425m	3.990ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.331m	9.080ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.903m	4.660ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.852m	3.098ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	8.286m	10.001ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	5.878m	6.035ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.544m	2.830ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.152m	2.681ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.929m	7.269ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.433m	6.418ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.921m	7.742ms	1	1	100.00
		chip_sw_lc_ctrl_transition	8.286m	10.001ms	1	1	100.00
		chip_prim_tl_access	1.611m	5.201ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	1.611m	5.201ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	16.266m	9.576ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	5.356m	8.066ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	21.021m	24.374ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	3.854m	7.375ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	7.382m	9.289ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	5.106m	6.957ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	19.265m	24.256ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	13.089m	13.781ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	6.451m	8.112ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	13.629m	13.753ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	4.062m	4.234ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	5.356m	8.066ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	4.021m	4.137ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	31.362m	37.103ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.838m	7.428ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.813m	5.408ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	19.983m	23.223ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.568m	8.150ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	14.789m	10.148ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	28.505m	24.990ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.365m	2.751ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	2.869m	3.421ms	0	1	0.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	4.978m	9.147ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	4.978m	9.147ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	14.789m	10.148ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	19.983m	23.223ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	4.062m	4.234ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.125m	6.143ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.256m	4.324ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.249m	4.335ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	2.717m	3.140ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	13.962m	13.607ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.791m	2.497ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	2.869m	3.421ms	0	1	0.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	11.974m	6.586ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.789m	4.631ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.279m	4.179ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.810m	3.405ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.852m	3.098ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.249m	4.335ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.249m	4.335ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	5.259m	5.984ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	15.083m	13.856ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.256m	4.324ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	4.888m	5.079ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.008m	5.936ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	2.821m	4.074ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	7.950m	26.891ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	10.017m	5.400ms	1	1	100.00
		chip_plic_all_irqs_10	4.387m	4.190ms	1	1	100.00
		chip_plic_all_irqs_20	6.048m	4.517ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.217m	2.953ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	3.106m	3.005ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	37.554m	14.745ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	8.096m	7.018ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.111m	3.703ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.574m	3.485ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	3.093m	3.171ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	5.903m	4.660ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.677m	5.008ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	4.328m	7.433ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	5.244m	6.531ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	8.474m	8.483ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	2.869m	3.421ms	0	1	0.00
		chip_sw_data_integrity_escalation	6.232m	4.909ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.568m	8.150ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	14.966m	22.291ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.731m	2.311ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.733m	3.305ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.699m	4.999ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	14.966m	22.291ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	14.966m	22.291ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	38.201m	21.272ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	38.201m	21.272ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	5.123m	5.865ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	6.142m	18.610ms	1	1	100.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.459m	2.793ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	3.094m	3.532ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.228m	3.208ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.937m	3.934ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	16.159m	8.574ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.297h	31.647ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	27.002m	12.073ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.340m	3.014ms	1	1	100.00
V2		TOTAL			241	275	87.64
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.447m	2.433ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.429m	2.433ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.447h	71.875ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	5.680m	3.813ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	17.665m	10.880ms	1	1	100.00
		rom_e2e_jtag_debug_dev	14.844m	11.603ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.625m	11.978ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.754m	4.405ms	1	1	100.00
		rom_e2e_jtag_inject_dev	3.094m	5.006ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.499m	4.174ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	12.329s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.721m	5.324ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.959m	2.936ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	14.339m	6.212ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	13.805m	6.432ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.889m	2.234ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.896m	4.995ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.002m	1.860ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	6.051m	4.767ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.515m	4.822ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	5.455m	4.534ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	14.789m	10.148ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	17.665m	10.880ms	1	1	100.00
		rom_e2e_jtag_debug_dev	14.844m	11.603ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.625m	11.978ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	4.653m	5.536ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	2.869m	3.421ms	0	1	0.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.405h	38.477ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.405h	38.477ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.760m	3.697ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.068m	4.059ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	47.415m	18.744ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	2.532m	2.560ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.285m	5.886ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.194m	2.667ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.365m	3.599ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.891m	4.306ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	18.228s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	3.065m	2.409ms	1	1	100.00
		TOTAL			286	325	88.00

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.69095522984974570222943165525832422283472945956436949942647968965164246580190
    Line 649, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.25576955644161324019330618244990013046875879087596409199300896760346599337409
    Line 687, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.42713639979027399965623662174552194465881006248078309012020531878835837253789
    Line 738, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.4539098711197781137779907253936668016915501357911655827815391802673000154271
    Line 693, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.51651231499393404882803174228196530874036535772397319938184419877045868712159
    Line 698, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.12387943269752433222715557850465169813736736661661758172326525978876654391140
    Line 611, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.103672425183693886323088583110707214576697579142837684551744380758158721978787
    Line 611, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.58808169386854059990326576997509185545785575173010166846025892245416935790193
    Line 601, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.76173426871389783044683215029676534649944478674037791174291997312614351964688
    Line 726, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.80625751763831505340922480610852577580543540929661781974189713613875823561339
    Line 715, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.98868642414910154542417526065950509282259939578226566800345221663308917989025
    Line 777, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.28187143497044439596805185567950173272288771107350472728809728084919867765593
    Line 688, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.6039813389537822862118401042414255120927724385227298388902331262438084308301
    Line 675, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.100883180526659041701219972164259624513521445534088935015264290109851035189516
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.145s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.58503364126393834257343200098903699284770879348581106208950305398814509996544
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 1.611s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.15384079151616510989525214069392970126717851835362128349427805050487840265034
    Line 823, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.32051802050719936729407458831399011247717841610581209600733918303249662653536
    Line 777, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.38572106260709859376600985504272547885548084597659086181664073521575370585255
    Line 1049, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.72143308399342368999288603659526351182881937099276215605758695213486302036848
    Line 814, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:634)] CHECK-fail: Unexpected mtval: expected *, got * has 1 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 0.chip_sw_all_escalation_resets.2620476674107341315924874318964325591436622064359035478566080301285280657810
    Line 514, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3420.796490 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:634)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 3420.796490 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.88292229586857796848476913966842335970279732524761775504746581122268846555372
    Line 438, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3703.112012 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3703.112012 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@79357) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.90003266100424994672433815220288997379291057978639707443861150417990114384505
Line 444, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4335.110004 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@79357) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4335.110004 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.57513960659977367875843815025886231356779676435177547667026545425495371451711
    Line 408, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3299.507750 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 3299.507750 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.24970601308491581905428798198500631804885083977587941250874628053493983886147
    Line 412, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2728.586602 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2728.586602 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.88133144159255997892299762870588786987290484829008951362385561241849311252916
    Line 407, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2765.885755 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 2765.885755 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33497) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.98061307100896907678752396361539974689888433078889055690217820615296545166588
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2571.152300 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33497) { a_addr: 'h1041c  a_data: 'h75a501d  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h34  a_opcode: 'h4  a_user: 'h1a942  d_param: 'h0  d_source: 'h34  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2571.152300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.81417813325490296069152181584011631144093848703609900144568709943773003154613
    Line 412, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2432.680442 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2432.680442 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.86411707236544247912088236695546577409158767806575156800150554814300529516998
    Line 422, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3734.565000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3734.565000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.2616568802619158561418605055552460892070957292691917797399172417006828527559
    Line 426, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3248.572000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3248.572000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.82473063113901724863375408949332583629836472540228107009692606046907188716433
    Line 476, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3813.139347 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3813.139347 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.94288900615654208894253797913003852834461056010695824689253361058923919169629
    Line 667, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.26395594031012444581430092017478393685007911035750577203155266672094790197245
    Line 787, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32213) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.53667267895200376217502248843782638509611323510009400450658251863906529451878
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2862.201976 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32213) { a_addr: 'h107f8  a_data: 'h1e47b805  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h14  a_opcode: 'h4  a_user: 'h1a962  d_param: 'h0  d_source: 'h14  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2862.201976 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---