ADC_CTRL Simulation Results

Wednesday April 23 2025 18:35:14 UTC

GitHub Revision: 856cba6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	5.950s	5.854ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.510s	621.496us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.190s	381.399us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	11.320s	14.797ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.330s	1.045ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.370s	404.665us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.190s	381.399us	1	1	100.00
		adc_ctrl_csr_aliasing	3.330s	1.045ms	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	4.631m	329.269ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	14.731m	489.033ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	58.420s	160.692ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	4.829m	165.911ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	3.922m	540.487ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	2.897m	414.908ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	4.609m	507.294ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	5.322m	180.251ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	6.720s	3.246ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.130m	44.229ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	1.986m	69.711ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	12.721m	496.027ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.730s	398.251us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	2.290s	474.004us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.480s	339.982us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.480s	339.982us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.510s	621.496us	1	1	100.00
		adc_ctrl_csr_rw	2.190s	381.399us	1	1	100.00
		adc_ctrl_csr_aliasing	3.330s	1.045ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	6.240s	4.897ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.510s	621.496us	1	1	100.00
		adc_ctrl_csr_rw	2.190s	381.399us	1	1	100.00
		adc_ctrl_csr_aliasing	3.330s	1.045ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	6.240s	4.897ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	5.760s	8.218ms	1	1	100.00
		adc_ctrl_tl_intg_err	6.130s	4.608ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	6.130s	4.608ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	9.310s	7.097ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00