AES/UNMASKED Simulation Results

Wednesday April 23 2025 18:35:14 UTC

GitHub Revision: 856cba6

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	66.354us	1	1	100.00
V1	smoke	aes_smoke	5.000s	68.567us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	58.188us	1	1	100.00
V1	csr_rw	aes_csr_rw	4.000s	115.494us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	7.000s	1.024ms	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	474.105us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	73.885us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	115.494us	1	1	100.00
		aes_csr_aliasing	6.000s	474.105us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	5.000s	68.567us	1	1	100.00
		aes_config_error	5.000s	135.686us	1	1	100.00
		aes_stress	5.000s	164.980us	1	1	100.00
V2	key_length	aes_smoke	5.000s	68.567us	1	1	100.00
		aes_config_error	5.000s	135.686us	1	1	100.00
		aes_stress	5.000s	164.980us	1	1	100.00
V2	back2back	aes_stress	5.000s	164.980us	1	1	100.00
		aes_b2b	9.000s	209.085us	1	1	100.00
V2	backpressure	aes_stress	5.000s	164.980us	1	1	100.00
V2	multi_message	aes_smoke	5.000s	68.567us	1	1	100.00
		aes_config_error	5.000s	135.686us	1	1	100.00
		aes_stress	5.000s	164.980us	1	1	100.00
		aes_alert_reset	4.000s	132.214us	1	1	100.00
V2	failure_test	aes_man_cfg_err	5.000s	103.692us	1	1	100.00
		aes_config_error	5.000s	135.686us	1	1	100.00
		aes_alert_reset	4.000s	132.214us	1	1	100.00
V2	trigger_clear_test	aes_clear	5.000s	238.622us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	619.906us	1	1	100.00
V2	reset_recovery	aes_alert_reset	4.000s	132.214us	1	1	100.00
V2	stress	aes_stress	5.000s	164.980us	1	1	100.00
V2	sideload	aes_stress	5.000s	164.980us	1	1	100.00
		aes_sideload	5.000s	70.618us	1	1	100.00
V2	deinitialization	aes_deinit	6.000s	155.161us	1	1	100.00
V2	stress_all	aes_stress_all	3.067m	10.096ms	0	1	0.00
V2	alert_test	aes_alert_test	4.000s	68.527us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	4.000s	455.761us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	4.000s	455.761us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	58.188us	1	1	100.00
		aes_csr_rw	4.000s	115.494us	1	1	100.00
		aes_csr_aliasing	6.000s	474.105us	1	1	100.00
		aes_same_csr_outstanding	6.000s	80.486us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	58.188us	1	1	100.00
		aes_csr_rw	4.000s	115.494us	1	1	100.00
		aes_csr_aliasing	6.000s	474.105us	1	1	100.00
		aes_same_csr_outstanding	6.000s	80.486us	1	1	100.00
V2		TOTAL			12	13	92.31
V2S	reseeding	aes_reseed	4.000s	66.934us	1	1	100.00
V2S	fault_inject	aes_fi	5.000s	233.643us	1	1	100.00
		aes_control_fi	4.000s	49.562us	1	1	100.00
		aes_cipher_fi	5.000s	53.335us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	116.151us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	116.151us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	116.151us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	116.151us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	102.175us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	342.093us	1	1	100.00
		aes_tl_intg_err	5.000s	193.751us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	193.751us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	4.000s	132.214us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	116.151us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	5.000s	68.567us	1	1	100.00
		aes_stress	5.000s	164.980us	1	1	100.00
		aes_alert_reset	4.000s	132.214us	1	1	100.00
		aes_core_fi	5.000s	119.990us	1	1	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	116.151us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	61.999us	1	1	100.00
		aes_stress	5.000s	164.980us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	5.000s	164.980us	1	1	100.00
		aes_sideload	5.000s	70.618us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	61.999us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	61.999us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	61.999us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	61.999us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	61.999us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	5.000s	164.980us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	5.000s	164.980us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	5.000s	233.643us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	5.000s	233.643us	1	1	100.00
		aes_control_fi	4.000s	49.562us	1	1	100.00
		aes_cipher_fi	5.000s	53.335us	1	1	100.00
		aes_ctr_fi	5.000s	53.664us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	5.000s	233.643us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	5.000s	233.643us	1	1	100.00
		aes_control_fi	4.000s	49.562us	1	1	100.00
		aes_cipher_fi	5.000s	53.335us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	5.000s	53.335us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	5.000s	233.643us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	5.000s	233.643us	1	1	100.00
		aes_control_fi	4.000s	49.562us	1	1	100.00
		aes_ctr_fi	5.000s	53.664us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	5.000s	233.643us	1	1	100.00
		aes_control_fi	4.000s	49.562us	1	1	100.00
		aes_cipher_fi	5.000s	53.335us	1	1	100.00
		aes_ctr_fi	5.000s	53.664us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	4.000s	132.214us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	5.000s	233.643us	1	1	100.00
		aes_control_fi	4.000s	49.562us	1	1	100.00
		aes_cipher_fi	5.000s	53.335us	1	1	100.00
		aes_ctr_fi	5.000s	53.664us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	5.000s	233.643us	1	1	100.00
		aes_control_fi	4.000s	49.562us	1	1	100.00
		aes_cipher_fi	5.000s	53.335us	1	1	100.00
		aes_ctr_fi	5.000s	53.664us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	5.000s	233.643us	1	1	100.00
		aes_control_fi	4.000s	49.562us	1	1	100.00
		aes_ctr_fi	5.000s	53.664us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	5.000s	233.643us	1	1	100.00
		aes_control_fi	4.000s	49.562us	1	1	100.00
		aes_cipher_fi	5.000s	53.335us	1	1	100.00
V2S		TOTAL			11	11	100.00
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	12.000s	947.843us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			30	32	93.75

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=22) has 1 failures:

  • Test aes_stress_all has 1 failures.

    • 0.aes_stress_all.9452955285237741056564222401528518288091129305786109719990051643831959640187
      Line 2460619, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all/latest/run.log

        UVM_FATAL @ 10096284057 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xf9fc7e84, Comparison=CompareOpEq, exp_data=0x1, call_count=22)
        UVM_INFO @ 10096284057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:

  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.35838734150369471537357915337407221994582588285660838026108377429299341082328
      Line 562, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 947842942 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
        UVM_INFO @ 947842942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---