HMAC Simulation Results

Wednesday April 23 2025 18:35:14 UTC

GitHub Revision: 856cba6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 3.940s 702.922us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.640s 67.697us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.640s 53.187us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 4.810s 531.393us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 3.080s 60.977us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.800s 48.873us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.640s 53.187us 1 1 100.00
hmac_csr_aliasing 3.080s 60.977us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 1.247m 17.371ms 1 1 100.00
V2 back_pressure hmac_back_pressure 56.100s 1.529ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.890s 193.744us 1 1 100.00
hmac_test_sha384_vectors 6.186m 52.290ms 1 1 100.00
hmac_test_sha512_vectors 18.850s 238.377us 1 1 100.00
hmac_test_hmac256_vectors 8.720s 285.934us 1 1 100.00
hmac_test_hmac384_vectors 7.010s 370.238us 1 1 100.00
hmac_test_hmac512_vectors 6.360s 262.314us 1 1 100.00
V2 burst_wr hmac_burst_wr 12.410s 2.139ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 1.860s 62.068us 1 1 100.00
V2 error hmac_error 33.300s 3.430ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 7.080s 2.555ms 1 1 100.00
V2 save_and_restore hmac_smoke 3.940s 702.922us 1 1 100.00
hmac_long_msg 1.247m 17.371ms 1 1 100.00
hmac_back_pressure 56.100s 1.529ms 1 1 100.00
hmac_datapath_stress 1.860s 62.068us 1 1 100.00
hmac_burst_wr 12.410s 2.139ms 1 1 100.00
hmac_stress_all 1.982m 8.916ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 3.940s 702.922us 1 1 100.00
hmac_long_msg 1.247m 17.371ms 1 1 100.00
hmac_back_pressure 56.100s 1.529ms 1 1 100.00
hmac_datapath_stress 1.860s 62.068us 1 1 100.00
hmac_wipe_secret 7.080s 2.555ms 1 1 100.00
hmac_test_sha256_vectors 8.890s 193.744us 1 1 100.00
hmac_test_sha384_vectors 6.186m 52.290ms 1 1 100.00
hmac_test_sha512_vectors 18.850s 238.377us 1 1 100.00
hmac_test_hmac256_vectors 8.720s 285.934us 1 1 100.00
hmac_test_hmac384_vectors 7.010s 370.238us 1 1 100.00
hmac_test_hmac512_vectors 6.360s 262.314us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 3.940s 702.922us 1 1 100.00
hmac_long_msg 1.247m 17.371ms 1 1 100.00
hmac_back_pressure 56.100s 1.529ms 1 1 100.00
hmac_datapath_stress 1.860s 62.068us 1 1 100.00
hmac_burst_wr 12.410s 2.139ms 1 1 100.00
hmac_error 33.300s 3.430ms 1 1 100.00
hmac_wipe_secret 7.080s 2.555ms 1 1 100.00
hmac_test_sha256_vectors 8.890s 193.744us 1 1 100.00
hmac_test_sha384_vectors 6.186m 52.290ms 1 1 100.00
hmac_test_sha512_vectors 18.850s 238.377us 1 1 100.00
hmac_test_hmac256_vectors 8.720s 285.934us 1 1 100.00
hmac_test_hmac384_vectors 7.010s 370.238us 1 1 100.00
hmac_test_hmac512_vectors 6.360s 262.314us 1 1 100.00
hmac_stress_all 1.982m 8.916ms 1 1 100.00
V2 stress_all hmac_stress_all 1.982m 8.916ms 1 1 100.00
V2 alert_test hmac_alert_test 1.480s 11.358us 1 1 100.00
V2 intr_test hmac_intr_test 1.460s 41.037us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.350s 150.044us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.350s 150.044us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.640s 67.697us 1 1 100.00
hmac_csr_rw 1.640s 53.187us 1 1 100.00
hmac_csr_aliasing 3.080s 60.977us 1 1 100.00
hmac_same_csr_outstanding 2.370s 52.932us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.640s 67.697us 1 1 100.00
hmac_csr_rw 1.640s 53.187us 1 1 100.00
hmac_csr_aliasing 3.080s 60.977us 1 1 100.00
hmac_same_csr_outstanding 2.370s 52.932us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.790s 280.294us 1 1 100.00
hmac_tl_intg_err 2.240s 722.354us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.240s 722.354us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 3.940s 702.922us 1 1 100.00
V3 stress_reset hmac_stress_reset 3.990s 876.898us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 2.514m 16.473ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.770s 29.251us 1 1 100.00
TOTAL 28 28 100.00