I2C Simulation Results

Wednesday April 23 2025 18:35:14 UTC

GitHub Revision: `856cba6`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	41.800s	5.436ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	8.310s	2.655ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.610s	19.189us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.590s	70.431us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.230s	194.686us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.470s	193.476us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.040s	27.902us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.590s	70.431us	1	1	100.00
		i2c_csr_aliasing	2.470s	193.476us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	5.210s	217.427us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	1.809m	58.232ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	7.790s	3.461ms	1	1	100.00
V2	host_override	i2c_host_override	1.470s	43.748us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.343m	18.083ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.820m	2.589ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.820s	334.089us	1	1	100.00
		i2c_host_fifo_fmt_empty	6.100s	332.673us	1	1	100.00
		i2c_host_fifo_reset_rx	3.700s	166.390us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	33.470s	2.089ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	12.760s	3.810ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	3.040s	465.617us	1	1	100.00
V2	target_glitch	i2c_target_glitch	7.580s	3.741ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	27.660s	33.761ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.840s	3.139ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	53.120s	7.278ms	1	1	100.00
		i2c_target_intr_smoke	8.360s	1.328ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.080s	343.928us	1	1	100.00
		i2c_target_fifo_reset_tx	2.060s	774.413us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	7.231m	47.294ms	1	1	100.00
		i2c_target_stress_rd	53.120s	7.278ms	1	1	100.00
		i2c_target_intr_stress_wr	1.116m	18.783ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.000s	10.344ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	2.310s	324.951us	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.290s	1.655ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	18.380s	10.190ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.800s	2.550ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.160s	143.469us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	7.790s	3.461ms	1	1	100.00
		i2c_host_perf_precise	2.180s	137.599us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	12.760s	3.810ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.850s	154.018us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.960s	5.581ms	1	1	100.00
		i2c_target_nack_acqfull_addr	3.160s	989.355us	1	1	100.00
		i2c_target_nack_txstretch	2.120s	147.068us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	11.350s	1.536ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.290s	4.527ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.580s	46.036us	1	1	100.00
V2	intr_test	i2c_intr_test	1.710s	26.391us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.280s	65.403us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.280s	65.403us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.610s	19.189us	1	1	100.00
		i2c_csr_rw	1.590s	70.431us	1	1	100.00
		i2c_csr_aliasing	2.470s	193.476us	1	1	100.00
		i2c_same_csr_outstanding	1.710s	335.531us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.610s	19.189us	1	1	100.00
		i2c_csr_rw	1.590s	70.431us	1	1	100.00
		i2c_csr_aliasing	2.470s	193.476us	1	1	100.00
		i2c_same_csr_outstanding	1.710s	335.531us	1	1	100.00
V2		TOTAL			36	38	94.74
V2S	tl_intg_err	i2c_tl_intg_err	2.920s	90.908us	1	1	100.00
		i2c_sec_cm	1.930s	44.080us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.920s	90.908us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	34.830s	1.078ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.260s	877.701us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	21.040s	3.260ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			45	50	90.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.112020055322283199951535307149698259340939304559623253749416714347822381854320
    Line 94, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1078134110 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1078134110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.49511376132666971615965111494628675489661921289168732575511848549962600751958
    Line 119, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3259546120 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3259546120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.104901299861703391990064492847085315677207142094814967969904389507122364216873
Line 182, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 58231869108 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @1348556

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.53237523026153379530913220777103723101507818661814117896394513117090589925907
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 877700758 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (0 [0x0] vs 209 [0xd1])
  UVM_INFO @ 877700758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:
- Test i2c_target_hrst has 1 failures.
  - 0.i2c_target_hrst.49388536310033012858839012404802340923292755877453499286306402314604516314035
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10190360191 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10190360191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```