KEYMGR Simulation Results

Wednesday April 23 2025 18:35:14 UTC

GitHub Revision: 856cba6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	3.900s	353.046us	1	1	100.00
V1	random	keymgr_random	3.720s	192.926us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.740s	297.389us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.840s	16.265us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	17.070s	3.450ms	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	7.290s	579.455us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.290s	39.151us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.840s	16.265us	1	1	100.00
		keymgr_csr_aliasing	7.290s	579.455us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	9.200s	274.150us	1	1	100.00
V2	sideload	keymgr_sideload	10.130s	1.036ms	1	1	100.00
		keymgr_sideload_kmac	3.400s	76.899us	1	1	100.00
		keymgr_sideload_aes	3.400s	182.575us	1	1	100.00
		keymgr_sideload_otbn	2.900s	55.581us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.200s	148.785us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.660s	172.063us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	2.990s	39.664us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	3.210s	33.422us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	26.990s	4.478ms	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.530s	118.166us	1	1	100.00
V2	stress_all	keymgr_stress_all	23.700s	1.020ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.780s	25.849us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.870s	16.385us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.150s	437.860us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.150s	437.860us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.740s	297.389us	1	1	100.00
		keymgr_csr_rw	1.840s	16.265us	1	1	100.00
		keymgr_csr_aliasing	7.290s	579.455us	1	1	100.00
		keymgr_same_csr_outstanding	2.660s	44.589us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.740s	297.389us	1	1	100.00
		keymgr_csr_rw	1.840s	16.265us	1	1	100.00
		keymgr_csr_aliasing	7.290s	579.455us	1	1	100.00
		keymgr_same_csr_outstanding	2.660s	44.589us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	8.180s	1.860ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	8.180s	1.860ms	1	1	100.00
		keymgr_tl_intg_err	5.670s	153.950us	0	1	0.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.670s	105.472us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.670s	105.472us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.670s	105.472us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.670s	105.472us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	6.970s	174.949us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	8.180s	1.860ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	8.180s	1.860ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	5.670s	153.950us	0	1	0.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.670s	105.472us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	9.200s	274.150us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	3.720s	192.926us	1	1	100.00
		keymgr_csr_rw	1.840s	16.265us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	3.720s	192.926us	1	1	100.00
		keymgr_csr_rw	1.840s	16.265us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	3.720s	192.926us	1	1	100.00
		keymgr_csr_rw	1.840s	16.265us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.660s	172.063us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	26.990s	4.478ms	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	26.990s	4.478ms	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	3.720s	192.926us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	1.710s	7.500us	0	1	0.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	8.180s	1.860ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	8.180s	1.860ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	8.180s	1.860ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	3.480s	138.062us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.660s	172.063us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	8.180s	1.860ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	8.180s	1.860ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	8.180s	1.860ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	3.480s	138.062us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	3.480s	138.062us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	8.180s	1.860ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	3.480s	138.062us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	8.180s	1.860ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	3.480s	138.062us	1	1	100.00
V2S		TOTAL			4	6	66.67
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	6.610s	136.950us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			28	30	93.33

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:349) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 1 failures:

  • Test keymgr_sideload_protect has 1 failures.

    • 0.keymgr_sideload_protect.77951536132474648232144164489087033978357561849064286175647592624114208307726
      Line 138, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_sideload_protect/latest/run.log

        UVM_ERROR @   7500066 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
        UVM_INFO @   7500066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test keymgr_tl_intg_err has 1 failures.

    • 0.keymgr_tl_intg_err.68861142774086995090160153947648893634250399529497654870181248954255954178348
      Line 208, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[5] & 'hffffffff)))'
        UVM_ERROR @ 153950299 ps: (keymgr_csr_assert_fpv.sv:391) [ASSERT FAILED] sealing_sw_binding_0_rd_A
        UVM_INFO @ 153950299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---