KMAC/MASKED Simulation Results

Wednesday April 23 2025 18:35:14 UTC

GitHub Revision: 856cba6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	56.810s	6.100ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.850s	92.770us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.660s	71.739us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.080s	151.275us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	5.230s	205.199us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.110s	590.962us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.660s	71.739us	1	1	100.00
		kmac_csr_aliasing	5.230s	205.199us	1	1	100.00
V1	mem_walk	kmac_mem_walk	2.040s	17.477us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.010s	40.895us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	12.414m	31.333ms	1	1	100.00
V2	burst_write	kmac_burst_write	12.137m	19.015ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	38.300s	5.087ms	1	1	100.00
		kmac_test_vectors_sha3_256	32.298m	356.736ms	1	1	100.00
		kmac_test_vectors_sha3_384	18.310m	13.300ms	1	1	100.00
		kmac_test_vectors_sha3_512	15.250s	4.140ms	1	1	100.00
		kmac_test_vectors_shake_128	29.317m	87.251ms	1	1	100.00
		kmac_test_vectors_shake_256	22.616m	69.281ms	1	1	100.00
		kmac_test_vectors_kmac	4.460s	196.893us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.980s	56.792us	1	1	100.00
V2	sideload	kmac_sideload	4.988m	23.533ms	1	1	100.00
V2	app	kmac_app	3.878m	12.998ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.368m	56.591ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.924m	17.285ms	1	1	100.00
V2	error	kmac_error	6.877m	31.248ms	1	1	100.00
V2	key_error	kmac_key_error	6.220s	596.409us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	4.890s	159.387us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	2.120s	92.478us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	8.150s	321.727us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	11.970s	5.559ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.320s	108.431us	1	1	100.00
V2	stress_all	kmac_stress_all	12.183m	154.579ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.710s	17.380us	1	1	100.00
V2	alert_test	kmac_alert_test	2.010s	35.637us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.250s	471.597us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.250s	471.597us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.850s	92.770us	1	1	100.00
		kmac_csr_rw	1.660s	71.739us	1	1	100.00
		kmac_csr_aliasing	5.230s	205.199us	1	1	100.00
		kmac_same_csr_outstanding	2.620s	41.142us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.850s	92.770us	1	1	100.00
		kmac_csr_rw	1.660s	71.739us	1	1	100.00
		kmac_csr_aliasing	5.230s	205.199us	1	1	100.00
		kmac_same_csr_outstanding	2.620s	41.142us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.520s	73.100us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.520s	73.100us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.520s	73.100us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.520s	73.100us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.870s	93.095us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	50.680s	40.247ms	1	1	100.00
		kmac_tl_intg_err	3.290s	751.712us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.290s	751.712us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.320s	108.431us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	56.810s	6.100ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	4.988m	23.533ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.520s	73.100us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	50.680s	40.247ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	50.680s	40.247ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	50.680s	40.247ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	56.810s	6.100ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.320s	108.431us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	50.680s	40.247ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.353m	7.877ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	56.810s	6.100ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	50.900s	2.629ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.30179760172518332695797821020924880565112881586149514147058602574399848103306
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[39] & 'hffffffff)))'
        UVM_ERROR @  93094877 ps: (kmac_csr_assert_fpv.sv:492) [ASSERT FAILED] prefix_0_rd_A
        UVM_INFO @  93094877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---