KMAC/UNMASKED Simulation Results

Wednesday April 23 2025 18:35:14 UTC

GitHub Revision: 856cba6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	27.660s	3.795ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.850s	65.825us	1	1	100.00
V1	csr_rw	kmac_csr_rw	2.000s	29.634us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.410s	682.099us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.470s	1.015ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.430s	70.932us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.000s	29.634us	1	1	100.00
		kmac_csr_aliasing	4.470s	1.015ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.660s	26.208us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.970s	55.037us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	21.225m	19.112ms	1	1	100.00
V2	burst_write	kmac_burst_write	1.162m	2.277ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	33.370s	31.863ms	1	1	100.00
		kmac_test_vectors_sha3_256	22.676m	75.500ms	1	1	100.00
		kmac_test_vectors_sha3_384	21.130s	7.206ms	1	1	100.00
		kmac_test_vectors_sha3_512	8.830m	42.509ms	1	1	100.00
		kmac_test_vectors_shake_128	2.521m	27.966ms	1	1	100.00
		kmac_test_vectors_shake_256	21.755m	224.079ms	1	1	100.00
		kmac_test_vectors_kmac	2.990s	149.456us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.300s	318.955us	1	1	100.00
V2	sideload	kmac_sideload	50.610s	9.268ms	1	1	100.00
V2	app	kmac_app	1.207m	26.277ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.608m	48.738ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.194m	3.219ms	1	1	100.00
V2	error	kmac_error	33.810s	931.030us	1	1	100.00
V2	key_error	kmac_key_error	6.550s	1.452ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	42.530s	10.112ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	23.210s	1.685ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	20.980s	1.568ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	24.070s	12.898ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.870s	68.577us	1	1	100.00
V2	stress_all	kmac_stress_all	24.897m	96.740ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.710s	42.385us	1	1	100.00
V2	alert_test	kmac_alert_test	1.650s	45.468us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.570s	67.674us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.570s	67.674us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.850s	65.825us	1	1	100.00
		kmac_csr_rw	2.000s	29.634us	1	1	100.00
		kmac_csr_aliasing	4.470s	1.015ms	1	1	100.00
		kmac_same_csr_outstanding	2.740s	570.716us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.850s	65.825us	1	1	100.00
		kmac_csr_rw	2.000s	29.634us	1	1	100.00
		kmac_csr_aliasing	4.470s	1.015ms	1	1	100.00
		kmac_same_csr_outstanding	2.740s	570.716us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.260s	442.412us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.260s	442.412us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.260s	442.412us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.260s	442.412us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.890s	475.886us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	48.860s	5.418ms	1	1	100.00
		kmac_tl_intg_err	2.790s	306.620us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.790s	306.620us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.870s	68.577us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	27.660s	3.795ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	50.610s	9.268ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.260s	442.412us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	48.860s	5.418ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	48.860s	5.418ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	48.860s	5.418ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	27.660s	3.795ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.870s	68.577us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	48.860s	5.418ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.205m	15.358ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	27.660s	3.795ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.149m	7.592ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.40156284958515399343742578823509260344629966021258258184403600692194867303964
      Line 80, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10112382501 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x1029b000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
        UVM_INFO @ 10112382501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.83072464320417952607529023609039830370582968322572955341797427239591307584425
      Line 132, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7592068495 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 7592068495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---