OTBN Simulation Results

Wednesday April 23 2025 18:35:14 UTC

GitHub Revision: 856cba6

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	13.000s	163.162us	1	1	100.00
V1	single_binary	otbn_single	10.000s	13.815us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	8.000s	17.788us	1	1	100.00
V1	csr_rw	otbn_csr_rw	6.000s	21.969us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	231.135us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	8.000s	17.737us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	7.000s	43.828us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	21.969us	1	1	100.00
		otbn_csr_aliasing	8.000s	17.737us	1	1	100.00
V1	mem_walk	otbn_mem_walk	32.000s	6.161ms	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	22.000s	581.416us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	23.000s	526.622us	1	1	100.00
V2	multi_error	otbn_multi_err	48.000s	352.392us	1	1	100.00
V2	back_to_back	otbn_multi	39.000s	122.757us	1	1	100.00
V2	stress_all	otbn_stress_all	1.217m	569.357us	1	1	100.00
V2	lc_escalation	otbn_escalate	10.000s	33.053us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	18.101us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	9.000s	15.671us	1	1	100.00
V2	alert_test	otbn_alert_test	7.000s	25.349us	1	1	100.00
V2	intr_test	otbn_intr_test	10.000s	16.158us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	17.000s	35.083us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	17.000s	35.083us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	8.000s	17.788us	1	1	100.00
		otbn_csr_rw	6.000s	21.969us	1	1	100.00
		otbn_csr_aliasing	8.000s	17.737us	1	1	100.00
		otbn_same_csr_outstanding	8.000s	82.705us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	8.000s	17.788us	1	1	100.00
		otbn_csr_rw	6.000s	21.969us	1	1	100.00
		otbn_csr_aliasing	8.000s	17.737us	1	1	100.00
		otbn_same_csr_outstanding	8.000s	82.705us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	12.000s	36.662us	1	1	100.00
		otbn_dmem_err	10.000s	69.340us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	16.000s	86.130us	1	1	100.00
		otbn_controller_ispr_rdata_err	15.000s	70.514us	1	1	100.00
		otbn_mac_bignum_acc_err	10.000s	73.206us	1	1	100.00
		otbn_urnd_err	8.000s	38.922us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	6.000s	72.373us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	9.000s	12.941us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	8.000s	39.007us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	13.000s	46.145us	0	1	0.00
		otbn_tl_intg_err	18.000s	121.834us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	1.350m	217.304us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	13.000s	46.145us	0	1	0.00
V2S	prim_count_check	otbn_sec_cm	13.000s	46.145us	0	1	0.00
V2S	sec_cm_mem_scramble	otbn_smoke	13.000s	163.162us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	10.000s	69.340us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	12.000s	36.662us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	18.000s	121.834us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	10.000s	33.053us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	12.000s	36.662us	1	1	100.00
		otbn_dmem_err	10.000s	69.340us	1	1	100.00
		otbn_zero_state_err_urnd	9.000s	18.101us	1	1	100.00
		otbn_illegal_mem_acc	6.000s	72.373us	1	1	100.00
		otbn_sec_cm	13.000s	46.145us	0	1	0.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	13.000s	46.145us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	otbn_single	10.000s	13.815us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	12.000s	36.662us	1	1	100.00
		otbn_dmem_err	10.000s	69.340us	1	1	100.00
		otbn_zero_state_err_urnd	9.000s	18.101us	1	1	100.00
		otbn_illegal_mem_acc	6.000s	72.373us	1	1	100.00
		otbn_sec_cm	13.000s	46.145us	0	1	0.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	13.000s	46.145us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	10.000s	33.053us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	12.000s	36.662us	1	1	100.00
		otbn_dmem_err	10.000s	69.340us	1	1	100.00
		otbn_zero_state_err_urnd	9.000s	18.101us	1	1	100.00
		otbn_illegal_mem_acc	6.000s	72.373us	1	1	100.00
		otbn_sec_cm	13.000s	46.145us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	13.000s	46.145us	0	1	0.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	10.000s	13.815us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	9.000s	22.414us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	13.000s	46.516us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	23.000s	70.972us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	23.000s	70.972us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	10.000s	56.195us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	13.000s	46.145us	0	1	0.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	13.000s	46.145us	0	1	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	9.000s	320.769us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	13.000s	46.145us	0	1	0.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	13.000s	46.145us	0	1	0.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	7.000s	138.327us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	7.000s	138.327us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	8.000s	28.849us	1	1	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	10.000s	13.815us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	10.000s	13.815us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	10.000s	13.815us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	39.000s	122.757us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	10.000s	13.815us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	10.000s	13.815us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	14.000s	151.417us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	10.000s	13.815us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	13.000s	46.145us	0	1	0.00
V2S		TOTAL			19	20	95.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	1.250m	594.488us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			40	41	97.56

Failure Buckets

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 1 failures:
  • Test otbn_sec_cm has 1 failures.

    • 0.otbn_sec_cm.77333121611573991014725645398742972208656132625018174730531595831780211193725
      Line 123, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 46144808 PS) Assertion tb.dut.ErrBitsKnown_A has failed
        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 46144808 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
        UVM_ERROR @  46144808 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
        UVM_INFO @  46144808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---