ROM_CTRL/32KB Simulation Results

Wednesday April 23 2025 18:35:14 UTC

GitHub Revision: 856cba6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 5.220s 557.777us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 6.110s 457.977us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.250s 123.517us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 4.480s 536.402us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.200s 123.816us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 5.590s 318.950us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.250s 123.517us 1 1 100.00
rom_ctrl_csr_aliasing 4.200s 123.816us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 3.640s 732.167us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 3.830s 418.887us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 5.960s 2.198ms 1 1 100.00
V2 stress_all rom_ctrl_stress_all 14.070s 751.229us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 8.280s 216.893us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.860s 165.490us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 5.600s 166.390us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 5.600s 166.390us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 6.110s 457.977us 1 1 100.00
rom_ctrl_csr_rw 4.250s 123.517us 1 1 100.00
rom_ctrl_csr_aliasing 4.200s 123.816us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.320s 297.239us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 6.110s 457.977us 1 1 100.00
rom_ctrl_csr_rw 4.250s 123.517us 1 1 100.00
rom_ctrl_csr_aliasing 4.200s 123.816us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.320s 297.239us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 21.490s 3.205ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 3.064m 694.085us 1 1 100.00
rom_ctrl_tl_intg_err 45.310s 527.308us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 3.064m 694.085us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 3.064m 694.085us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 3.064m 694.085us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 3.064m 694.085us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 5.220s 557.777us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 5.220s 557.777us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 5.220s 557.777us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 45.310s 527.308us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_kmac_err_chk 8.280s 216.893us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 21.490s 3.205ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 3.064m 694.085us 1 1 100.00
V2S TOTAL 3 4 75.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 31.740s 3.229ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 18 19 94.74

Failure Buckets