SPI_DEVICE/1R1W Simulation Results

Wednesday April 23 2025 18:35:14 UTC

GitHub Revision: 856cba6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	15.660s	2.200ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.130s	23.980us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.440s	83.356us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	10.680s	3.792ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	6.370s	1.234ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.540s	25.808us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.440s	83.356us	1	1	100.00
		spi_device_csr_aliasing	6.370s	1.234ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.470s	22.015us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.510s	660.715us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.510s	70.866us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.760s	5.869us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.600s	5.569us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.630s	28.332us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.630s	28.332us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	3.060s	364.856us	1	1	100.00
		spi_device_tpm_sts_read	1.790s	30.468us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	23.800s	5.979ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	2.570s	59.450us	1	1	100.00
		spi_device_flash_all	13.230s	4.412ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	8.410s	9.894ms	1	1	100.00
		spi_device_flash_all	13.230s	4.412ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	8.410s	9.894ms	1	1	100.00
		spi_device_flash_all	13.230s	4.412ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	13.230s	4.412ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.130s	113.161us	1	1	100.00
		spi_device_flash_all	13.230s	4.412ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.130s	113.161us	1	1	100.00
		spi_device_flash_all	13.230s	4.412ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.130s	113.161us	1	1	100.00
		spi_device_flash_all	13.230s	4.412ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.130s	113.161us	1	1	100.00
		spi_device_flash_all	13.230s	4.412ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.130s	113.161us	1	1	100.00
		spi_device_flash_all	13.230s	4.412ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	18.420s	19.400ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	18.700s	8.831ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	18.700s	8.831ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	18.700s	8.831ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	4.660s	348.080us	1	1	100.00
		spi_device_read_buffer_direct	10.660s	1.848ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	18.700s	8.831ms	1	1	100.00
		spi_device_flash_all	13.230s	4.412ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	13.230s	4.412ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	13.230s	4.412ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	5.510s	471.990us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	5.510s	471.990us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	15.660s	2.200ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.468m	215.755ms	1	1	100.00
V2	stress_all	spi_device_stress_all	5.227m	45.289ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.660s	16.039us	1	1	100.00
V2	intr_test	spi_device_intr_test	2.080s	61.660us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.920s	259.859us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.920s	259.859us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.130s	23.980us	1	1	100.00
		spi_device_csr_rw	2.440s	83.356us	1	1	100.00
		spi_device_csr_aliasing	6.370s	1.234ms	1	1	100.00
		spi_device_same_csr_outstanding	2.280s	118.418us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.130s	23.980us	1	1	100.00
		spi_device_csr_rw	2.440s	83.356us	1	1	100.00
		spi_device_csr_aliasing	6.370s	1.234ms	1	1	100.00
		spi_device_same_csr_outstanding	2.280s	118.418us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.410s	763.937us	1	1	100.00
		spi_device_tl_intg_err	15.780s	1.289ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	15.780s	1.289ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.425m	64.361ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.111115003017249835603157681919579709239476831727041645784256939153094835073399
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   3909416 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[97])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   3909416 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   3909416 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[993])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.49523004588385209524399868993519307870762220608924232780419522860951678584391
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   4762518 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4762518 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   4828518 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3f88cb [1111111000100011001011] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   4828518 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0x3f88cb [1111111000100011001011] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])