SPI_DEVICE/2P Simulation Results

Wednesday April 23 2025 18:35:14 UTC

GitHub Revision: 856cba6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	4.080m	87.060ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.160s	57.078us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.680s	260.822us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	23.760s	538.340us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	13.160s	777.067us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.510s	89.253us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.680s	260.822us	1	1	100.00
		spi_device_csr_aliasing	13.160s	777.067us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.530s	13.941us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.610s	71.788us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.780s	16.824us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.920s	25.550us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	1.590s	10.385us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.870s	152.835us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.870s	152.835us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	6.060s	4.266ms	1	1	100.00
		spi_device_tpm_sts_read	1.840s	57.786us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	17.420s	9.580ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	2.970s	113.242us	1	1	100.00
		spi_device_flash_all	1.535m	87.446ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	8.070s	5.196ms	1	1	100.00
		spi_device_flash_all	1.535m	87.446ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	8.070s	5.196ms	1	1	100.00
		spi_device_flash_all	1.535m	87.446ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.535m	87.446ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	16.200s	2.431ms	1	1	100.00
		spi_device_flash_all	1.535m	87.446ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	16.200s	2.431ms	1	1	100.00
		spi_device_flash_all	1.535m	87.446ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	16.200s	2.431ms	1	1	100.00
		spi_device_flash_all	1.535m	87.446ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	16.200s	2.431ms	1	1	100.00
		spi_device_flash_all	1.535m	87.446ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	16.200s	2.431ms	1	1	100.00
		spi_device_flash_all	1.535m	87.446ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	7.630s	12.304ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	30.370s	38.201ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	30.370s	38.201ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	30.370s	38.201ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	11.790s	335.717us	1	1	100.00
		spi_device_read_buffer_direct	4.180s	1.932ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	30.370s	38.201ms	1	1	100.00
		spi_device_flash_all	1.535m	87.446ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.535m	87.446ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.535m	87.446ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	12.170s	3.331ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	12.170s	3.331ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	4.080m	87.060ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	57.330s	15.550ms	1	1	100.00
V2	stress_all	spi_device_stress_all	3.099m	19.242ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.720s	13.081us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.850s	14.397us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.440s	94.375us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.440s	94.375us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.160s	57.078us	1	1	100.00
		spi_device_csr_rw	2.680s	260.822us	1	1	100.00
		spi_device_csr_aliasing	13.160s	777.067us	1	1	100.00
		spi_device_same_csr_outstanding	2.650s	49.722us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.160s	57.078us	1	1	100.00
		spi_device_csr_rw	2.680s	260.822us	1	1	100.00
		spi_device_csr_aliasing	13.160s	777.067us	1	1	100.00
		spi_device_same_csr_outstanding	2.650s	49.722us	1	1	100.00
V2		TOTAL			21	22	95.45
V2S	tl_intg_err	spi_device_sec_cm	1.950s	409.975us	1	1	100.00
		spi_device_tl_intg_err	14.930s	4.150ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	14.930s	4.150ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	4.991m	310.869ms	1	1	100.00
		TOTAL			32	33	96.97

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:
  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.2131997717441002094229884682598038651727611273650172600922494894331481589907
      Line 71, in log /nightly/runs/scratch/master/spi_device_2p-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   9591036 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   9591036 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   9688036 ps: (spi_device_ram_cfg_vseq.sv:23) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === dst_ram_cfg (0x47c66b [10001111100011001101011] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   9688036 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)