SPI_HOST Simulation Results

Wednesday April 23 2025 18:35:14 UTC

GitHub Revision: 856cba6

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	3.417m	13.550ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	21.358us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	17.944us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	413.392us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	51.556us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	32.146us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	17.944us	1	1	100.00
		spi_host_csr_aliasing	4.000s	51.556us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	16.152us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	57.989us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	4.000s	38.430us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	5.000s	136.693us	1	1	100.00
		spi_host_error_cmd	4.000s	17.616us	1	1	100.00
		spi_host_event	38.000s	1.297ms	1	1	100.00
V2	clock_rate	spi_host_speed	8.000s	371.845us	1	1	100.00
V2	speed	spi_host_speed	8.000s	371.845us	1	1	100.00
V2	chip_select_timing	spi_host_speed	8.000s	371.845us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	29.000s	1.060ms	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	192.576us	1	1	100.00
V2	cpol_cpha	spi_host_speed	8.000s	371.845us	1	1	100.00
V2	full_cycle	spi_host_speed	8.000s	371.845us	1	1	100.00
V2	duplex	spi_host_smoke	3.417m	13.550ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	3.417m	13.550ms	1	1	100.00
V2	stress_all	spi_host_stress_all	9.000s	1.336ms	1	1	100.00
V2	spien	spi_host_spien	8.000s	838.178us	1	1	100.00
V2	stall	spi_host_status_stall	10.000s	368.724us	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	17.000s	770.435us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	5.000s	136.693us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	88.005us	1	1	100.00
V2	intr_test	spi_host_intr_test	3.000s	20.971us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	57.389us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	57.389us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	21.358us	1	1	100.00
		spi_host_csr_rw	4.000s	17.944us	1	1	100.00
		spi_host_csr_aliasing	4.000s	51.556us	1	1	100.00
		spi_host_same_csr_outstanding	3.000s	26.749us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	21.358us	1	1	100.00
		spi_host_csr_rw	4.000s	17.944us	1	1	100.00
		spi_host_csr_aliasing	4.000s	51.556us	1	1	100.00
		spi_host_same_csr_outstanding	3.000s	26.749us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	5.000s	275.245us	1	1	100.00
		spi_host_sec_cm	4.000s	238.433us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	5.000s	275.245us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	35.283m	139.582ms	0	1	0.00
		TOTAL			25	26	96.15

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 0.spi_host_upper_range_clkdiv.40289850605302776687468475506612507164535447174724149755440423475720305246063
      Line 202, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 139581863314 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xbbc0f714, Comparison=CompareOpEq, exp_data=0x1, call_count=17)
        UVM_INFO @ 139581863314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---