SRAM_CTRL/MAIN Simulation Results

Wednesday April 23 2025 18:35:14 UTC

GitHub Revision: 856cba6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	6.860s	1.349ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.980s	33.888us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.050s	41.583us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.550s	652.388us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.940s	35.881us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.870s	382.029us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.050s	41.583us	1	1	100.00
		sram_ctrl_csr_aliasing	1.940s	35.881us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.156m	21.100ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.760m	9.726ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	2.707m	3.461ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.579m	3.532ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	19.512m	282.737ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	12.114m	61.686ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	47.940s	39.239ms	1	1	100.00
V2	executable	sram_ctrl_executable	10.087m	16.423ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	9.240s	5.555ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.896m	15.265ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	29.530s	838.408us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	51.220s	2.767ms	1	1	100.00
		sram_ctrl_throughput_w_readback	26.620s	841.015us	1	1	100.00
V2	regwen	sram_ctrl_regwen	2.115m	6.808ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.240s	1.403ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	2.694m	284.329ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.610s	109.863us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.540s	126.791us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.540s	126.791us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.980s	33.888us	1	1	100.00
		sram_ctrl_csr_rw	2.050s	41.583us	1	1	100.00
		sram_ctrl_csr_aliasing	1.940s	35.881us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.610s	51.268us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.980s	33.888us	1	1	100.00
		sram_ctrl_csr_rw	2.050s	41.583us	1	1	100.00
		sram_ctrl_csr_aliasing	1.940s	35.881us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.610s	51.268us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	18.380s	7.678ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.050s	4.227us	0	1	0.00
		sram_ctrl_tl_intg_err	2.400s	86.093us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.050s	4.227us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.400s	86.093us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	2.115m	6.808ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	2.115m	6.808ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.050s	41.583us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	10.087m	16.423ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	10.087m	16.423ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	10.087m	16.423ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	47.940s	39.239ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.260s	729.418us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	18.380s	7.678ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	9.190s	3.882ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	6.860s	1.349ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	6.860s	1.349ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	10.087m	16.423ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.050s	4.227us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	47.940s	39.239ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.050s	4.227us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.050s	4.227us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	6.860s	1.349ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.050s	4.227us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	18.860s	3.382ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.8372848982220052298911346839864209846844128206239833190915603683079076778989
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   4226843 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   4226843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---