SRAM_CTRL/RET Simulation Results

Wednesday April 23 2025 18:35:14 UTC

GitHub Revision: 856cba6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	10.770s	2.563ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.640s	30.018us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.600s	28.160us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.050s	456.685us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.650s	20.034us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.770s	106.551us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.600s	28.160us	1	1	100.00
		sram_ctrl_csr_aliasing	1.650s	20.034us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	8.530s	720.002us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.240s	116.896us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	5.399m	2.935ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.435m	17.702ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	58.120s	5.356ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	12.679m	19.115ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	4.840s	1.490ms	1	1	100.00
V2	executable	sram_ctrl_executable	7.360m	24.816ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	9.090s	1.838ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.355m	19.389ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	15.750s	114.112us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	33.950s	142.916us	1	1	100.00
		sram_ctrl_throughput_w_readback	2.440s	199.367us	1	1	100.00
V2	regwen	sram_ctrl_regwen	6.919m	39.012ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.660s	82.688us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	3.462m	16.818ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.710s	28.124us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.620s	218.132us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.620s	218.132us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.640s	30.018us	1	1	100.00
		sram_ctrl_csr_rw	1.600s	28.160us	1	1	100.00
		sram_ctrl_csr_aliasing	1.650s	20.034us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.550s	22.236us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.640s	30.018us	1	1	100.00
		sram_ctrl_csr_rw	1.600s	28.160us	1	1	100.00
		sram_ctrl_csr_aliasing	1.650s	20.034us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.550s	22.236us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.360s	411.030us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.470s	12.783us	0	1	0.00
		sram_ctrl_tl_intg_err	2.370s	192.349us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.470s	12.783us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.370s	192.349us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	6.919m	39.012ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	6.919m	39.012ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.600s	28.160us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	7.360m	24.816ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	7.360m	24.816ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	7.360m	24.816ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	4.840s	1.490ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.810s	102.548us	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.360s	411.030us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.710s	32.545us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	10.770s	2.563ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	10.770s	2.563ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	7.360m	24.816ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.470s	12.783us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	4.840s	1.490ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.470s	12.783us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.470s	12.783us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	10.770s	2.563ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.470s	12.783us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	5.112m	1.676ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.28811598462982829066426208540469145418528869527378810368109258247543299121673
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 102548007 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 102548007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.39335639625817574997538807072767041115419717311370323352456609636202240791258
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @  12783458 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  12783458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---