SYSRST_CTRL Simulation Results

Wednesday April 23 2025 18:35:14 UTC

GitHub Revision: 856cba6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	5.560s	2.113ms	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	2.660s	2.519ms	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	7.630s	2.398ms	1	1	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	3.200s	2.530ms	1	1	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	3.920s	4.051ms	1	1	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	2.620s	2.052ms	1	1	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	3.849m	75.769ms	1	1	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	7.080s	3.166ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	5.680s	2.034ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	2.620s	2.052ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	7.080s	3.166ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	6.478m	195.478ms	1	1	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	59.270s	113.767ms	1	1	100.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	2.540s	3.444ms	1	1	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	2.440s	2.651ms	1	1	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	4.500s	2.518ms	1	1	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	3.570s	2.057ms	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	19.347m	564.930ms	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	2.710s	2.635ms	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	2.470s	5.127ms	0	1	0.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	19.230s	37.643ms	1	1	100.00
V2	stress_all	sysrst_ctrl_stress_all	3.000s	6.841ms	1	1	100.00
V2	alert_test	sysrst_ctrl_alert_test	2.430s	2.028ms	1	1	100.00
V2	intr_test	sysrst_ctrl_intr_test	3.930s	2.021ms	1	1	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	3.620s	2.105ms	1	1	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	3.620s	2.105ms	1	1	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	3.920s	4.051ms	1	1	100.00
		sysrst_ctrl_csr_rw	2.620s	2.052ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	7.080s	3.166ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	15.520s	4.933ms	1	1	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	3.920s	4.051ms	1	1	100.00
		sysrst_ctrl_csr_rw	2.620s	2.052ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	7.080s	3.166ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	15.520s	4.933ms	1	1	100.00
V2		TOTAL			14	15	93.33
V2S	tl_intg_err	sysrst_ctrl_sec_cm	24.220s	22.024ms	1	1	100.00
		sysrst_ctrl_tl_intg_err	1.451m	42.367ms	1	1	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	1.451m	42.367ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	5.710s	3.914ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:251) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 1 failures:
  • Test sysrst_ctrl_ultra_low_pwr has 1 failures.

    • 0.sysrst_ctrl_ultra_low_pwr.52039063637617426319023425836032212314634998651400575286403082315318155868993
      Line 379, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest/run.log

        UVM_ERROR @ 5126864878 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_ERROR @ 5127137604 ps: (cip_base_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
        UVM_INFO @ 5127137604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---