UART Simulation Results

Wednesday April 23 2025 18:35:14 UTC

GitHub Revision: 856cba6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.940s	716.708us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.430s	14.106us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.450s	40.276us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.090s	136.654us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.510s	70.581us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.710s	73.456us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.450s	40.276us	1	1	100.00
		uart_csr_aliasing	1.510s	70.581us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	17.020s	231.686ms	1	1	100.00
V2	parity	uart_smoke	1.940s	716.708us	1	1	100.00
		uart_tx_rx	17.020s	231.686ms	1	1	100.00
V2	parity_error	uart_intr	25.610s	44.682ms	1	1	100.00
		uart_rx_parity_err	26.480s	48.077ms	1	1	100.00
V2	watermark	uart_tx_rx	17.020s	231.686ms	1	1	100.00
		uart_intr	25.610s	44.682ms	1	1	100.00
V2	fifo_full	uart_fifo_full	45.170s	39.815ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	25.780s	92.732ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	21.070s	135.516ms	1	1	100.00
V2	rx_frame_err	uart_intr	25.610s	44.682ms	1	1	100.00
V2	rx_break_err	uart_intr	25.610s	44.682ms	1	1	100.00
V2	rx_timeout	uart_intr	25.610s	44.682ms	1	1	100.00
V2	perf	uart_perf	5.677m	8.821ms	1	1	100.00
V2	sys_loopback	uart_loopback	11.920s	10.493ms	1	1	100.00
V2	line_loopback	uart_loopback	11.920s	10.493ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	1.119m	58.282ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	45.350s	80.555ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.080s	964.515us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	43.910s	6.901ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	57.370s	165.741ms	1	1	100.00
V2	stress_all	uart_stress_all	1.749m	169.386ms	1	1	100.00
V2	alert_test	uart_alert_test	1.540s	128.836us	1	1	100.00
V2	intr_test	uart_intr_test	1.340s	18.319us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.560s	388.828us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.560s	388.828us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.430s	14.106us	1	1	100.00
		uart_csr_rw	1.450s	40.276us	1	1	100.00
		uart_csr_aliasing	1.510s	70.581us	1	1	100.00
		uart_same_csr_outstanding	1.510s	64.828us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.430s	14.106us	1	1	100.00
		uart_csr_rw	1.450s	40.276us	1	1	100.00
		uart_csr_aliasing	1.510s	70.581us	1	1	100.00
		uart_same_csr_outstanding	1.510s	64.828us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.810s	319.133us	1	1	100.00
		uart_tl_intg_err	1.960s	353.991us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.960s	353.991us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	28.660s	15.429ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00