CHIP Simulation Results

Wednesday April 23 2025 18:35:14 UTC

GitHub Revision: `856cba6`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.914m	2.290ms	1	1	100.00
		chip_sw_example_rom	1.178m	2.345ms	1	1	100.00
		chip_sw_example_manufacturer	2.523m	2.727ms	1	1	100.00
		chip_sw_example_concurrency	2.161m	3.238ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	4.060m	5.628ms	1	1	100.00
V1	csr_rw	chip_csr_rw	6.527m	6.196ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	4.529m	5.936ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	59.436m	38.295ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	55.950s	2.321ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	59.436m	38.295ms	1	1	100.00
		chip_csr_rw	6.527m	6.196ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	10.460s	183.290us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.058m	3.792ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.058m	3.792ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.058m	3.792ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.183m	4.310ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.183m	4.310ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.160m	4.187ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.283m	3.585ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.570m	4.206ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	5.795m	3.671ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	4.402m	3.655ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	4.623m	4.669ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.863m	4.069ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.863m	4.069ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.617m	2.564ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.630m	3.459ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.959m	3.977ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	7.346m	7.726ms	1	1	100.00
		chip_tap_straps_testunlock0	1.469m	2.284ms	1	1	100.00
		chip_tap_straps_rma	4.679m	5.515ms	1	1	100.00
		chip_tap_straps_prod	5.304m	5.788ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.443m	3.214ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	11.579m	9.510ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.002m	5.362ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.002m	5.362ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	10.031m	8.240ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	32.936m	23.725ms	1	1	100.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.484m	4.848ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.866m	5.956ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	56.065m	18.698ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.227m	3.219ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	9.861m	6.693ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.345m	3.481ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	12.454m	8.775ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.575m	2.339ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.912m	4.651ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.569m	2.473ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.546m	2.241ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	7.209m	6.231ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.689m	5.058ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.728m	2.982ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.689m	5.058ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	1.751m	2.645ms	1	1	100.00
		chip_sw_aes_smoketest	2.699m	3.376ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.120m	3.326ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.977m	2.994ms	1	1	100.00
		chip_sw_csrng_smoketest	2.549m	2.921ms	1	1	100.00
		chip_sw_entropy_src_smoketest	4.999m	3.852ms	1	1	100.00
		chip_sw_gpio_smoketest	2.955m	2.791ms	1	1	100.00
		chip_sw_hmac_smoketest	2.872m	2.369ms	1	1	100.00
		chip_sw_kmac_smoketest	2.971m	3.000ms	1	1	100.00
		chip_sw_otbn_smoketest	9.959m	6.104ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.647m	4.574ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.188m	5.926ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.579m	2.515ms	1	1	100.00
		chip_sw_rv_timer_smoketest	3.038m	3.053ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.085m	2.388ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.124m	2.003ms	1	1	100.00
		chip_sw_uart_smoketest	2.646m	2.966ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.282m	2.724ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	5.760m	4.771ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.983h	61.688ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	40.618m	14.921ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.815m	5.168ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.202m	3.205ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.931m	3.223ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.789h	52.711ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.896h	55.618ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	43.630s	1.984ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	43.630s	1.984ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	59.436m	38.295ms	1	1	100.00
		chip_same_csr_outstanding	17.988m	14.763ms	1	1	100.00
		chip_csr_hw_reset	4.060m	5.628ms	1	1	100.00
		chip_csr_rw	6.527m	6.196ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	59.436m	38.295ms	1	1	100.00
		chip_same_csr_outstanding	17.988m	14.763ms	1	1	100.00
		chip_csr_hw_reset	4.060m	5.628ms	1	1	100.00
		chip_csr_rw	6.527m	6.196ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	19.170s	386.313us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	5.650s	45.863us	1	1	100.00
		xbar_smoke_large_delays	48.320s	8.228ms	1	1	100.00
		xbar_smoke_slow_rsp	38.730s	4.055ms	1	1	100.00
		xbar_random_zero_delays	19.240s	394.321us	1	1	100.00
		xbar_random_large_delays	2.304m	22.476ms	1	1	100.00
		xbar_random_slow_rsp	2.208m	15.854ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	28.130s	1.119ms	1	1	100.00
		xbar_error_and_unmapped_addr	26.070s	1.080ms	1	1	100.00
V2	xbar_error_cases	xbar_error_random	10.400s	131.474us	1	1	100.00
		xbar_error_and_unmapped_addr	26.070s	1.080ms	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	23.010s	543.440us	1	1	100.00
		xbar_access_same_device_slow_rsp	26.790s	2.728ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	13.150s	272.521us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	4.298m	12.652ms	1	1	100.00
		xbar_stress_all_with_error	2.528m	8.059ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	15.190s	303.241us	1	1	100.00
		xbar_stress_all_with_reset_error	3.013m	4.298ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	40.618m	14.921ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	34.766m	32.197ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	39.854m	14.642ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	32.289m	11.269ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	40.363m	14.972ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	42.150m	15.548ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	39.871m	15.425ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	39.359m	14.498ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	28.050s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	28.910s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	27.360s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	29.520s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	28.430s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	28.320s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	28.480s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	30.370s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	34.200s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	26.950s	10.120us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	26.620s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	26.300s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	25.320s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	29.080s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	28.210s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	28.480s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	25.490s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	26.520s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	25.770s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	26.360s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	26.300s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	29.020s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	25.670s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	25.610s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	27.460s	10.260us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	29.563m	10.595ms	1	1	100.00
		rom_e2e_asm_init_dev	39.014m	15.472ms	1	1	100.00
		rom_e2e_asm_init_prod	39.417m	15.475ms	1	1	100.00
		rom_e2e_asm_init_prod_end	38.797m	15.727ms	1	1	100.00
		rom_e2e_asm_init_rma	35.261m	15.530ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	36.334m	15.070ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	35.919m	15.089ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	37.201m	15.285ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	37.463m	15.768ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	6.321m	18.721ms	1	1	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	6.321m	18.721ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.252m	3.136ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.227m	3.219ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.817m	2.684ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.591m	2.942ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	28.098m	12.419ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.157m	3.188ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.952m	5.847ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	5.815m	5.708ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	8.460m	5.374ms	1	1	100.00
		chip_plic_all_irqs_10	4.110m	3.889ms	1	1	100.00
		chip_plic_all_irqs_20	5.846m	3.941ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	3.288m	3.593ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	12.682m	11.211ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	4.787m	5.011ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.472m	3.258ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	10.994m	12.392ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	21.185m	9.852ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	14.010m	7.320ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	12.602m	8.278ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	1.982h	254.683ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	4.118m	4.489ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.647m	4.574ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	4.118m	4.489ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.519m	9.952ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.519m	9.952ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	3.031m	6.266ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	5.215m	5.009ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.804m	6.407ms	1	1	100.00
		chip_sw_aes_idle	2.591m	2.942ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.689m	3.389ms	1	1	100.00
		chip_sw_kmac_idle	1.840m	2.393ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.912m	4.469ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	3.840m	4.338ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	3.558m	4.247ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.427m	4.819ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	14.543m	12.019ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.997m	4.133ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.529m	5.006ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.339m	4.310ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	4.983m	4.049ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.366m	3.692ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.686m	4.926ms	1	1	100.00
		chip_sw_ast_clk_outputs	10.031m	8.240ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	4.463m	4.997ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.339m	4.310ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	4.983m	4.049ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.484m	4.848ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.866m	5.956ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	56.065m	18.698ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.227m	3.219ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	9.861m	6.693ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.345m	3.481ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	12.454m	8.775ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.575m	2.339ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.912m	4.651ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.569m	2.473ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.912m	2.896ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.508m	4.267ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	11.472m	7.210ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	50.104m	25.049ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.359m	2.728ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	3.223m	3.226ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	11.199m	7.979ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.634m	2.905ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	4.917m	5.286ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	16.294m	24.016ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.427h	55.626ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	10.031m	8.240ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.172m	5.015ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.682m	3.213ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	5.815m	5.708ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	21.185m	9.852ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	14.965m	7.666ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.258m	2.282ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	4.951m	6.333ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.460m	3.251ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.070h	23.549ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	1.853m	2.590ms	1	1	100.00
		chip_sw_edn_entropy_reqs	12.480m	7.250ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	1.853m	2.590ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	14.965m	7.666ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.001m	2.741ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	19.389m	20.819ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.660m	5.574ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.866m	5.956ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	6.059m	3.663ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	6.484m	4.848ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	57.027m	43.946ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	19.389m	20.819ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.267m	3.518ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	10.534m	6.342ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.262m	5.212ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	57.027m	43.946ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.262m	5.212ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.262m	5.212ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	5.262m	5.212ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.262m	5.212ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	5.815m	5.708ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	3.166m	9.438ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.824m	5.371ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	6.540m	5.856ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	6.540m	5.856ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.816m	2.991ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.345m	3.481ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.689m	3.389ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	3.128m	2.883ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	11.759m	6.079ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	5.545m	5.283ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.364m	5.079ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	6.565m	4.615ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	3.877m	3.861ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	10.534m	6.342ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	12.454m	8.775ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	19.476m	10.750ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	28.098m	12.419ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	43.517m	13.507ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.502m	2.389ms	1	1	100.00
		chip_sw_kmac_mode_kmac	3.228m	2.871ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.575m	2.339ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	10.534m	6.342ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	5.002m	7.160ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.724m	3.571ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	20.779m	10.110ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	1.840m	2.393ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.952m	5.847ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	7.346m	7.726ms	1	1	100.00
		chip_tap_straps_rma	4.679m	5.515ms	1	1	100.00
		chip_tap_straps_prod	5.304m	5.788ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.570m	3.521ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	5.002m	7.160ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	5.002m	7.160ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	5.002m	7.160ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	12.450m	7.167ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	5.262m	5.212ms	1	1	100.00
		chip_sw_flash_rma_unlocked	57.027m	43.946ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.353m	3.330ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.207m	7.824ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.699m	6.429ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.021m	5.663ms	1	1	100.00
		chip_sw_lc_ctrl_transition	5.002m	7.160ms	1	1	100.00
		chip_sw_keymgr_key_derivation	10.534m	6.342ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	3.873m	9.829ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	5.302m	6.077ms	1	1	100.00
		chip_prim_tl_access	3.166m	9.438ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	4.463m	4.997ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.997m	4.133ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.529m	5.006ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.339m	4.310ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	4.983m	4.049ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.366m	3.692ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.686m	4.926ms	1	1	100.00
		chip_tap_straps_dev	7.346m	7.726ms	1	1	100.00
		chip_tap_straps_rma	4.679m	5.515ms	1	1	100.00
		chip_tap_straps_prod	5.304m	5.788ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.336m	11.435ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.312m	3.131ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.714m	3.649ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.573m	3.652ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.534m	3.354ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	22.137m	31.707ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.336m	11.435ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.087h	50.778ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.093h	47.407ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	8.568m	7.927ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	55.120m	47.710ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	22.137m	31.707ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.360m	2.330ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.101m	2.204ms	1	1	100.00
		rom_volatile_raw_unlock	1.179m	2.604ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	53.817m	17.102ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	56.065m	18.698ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.804m	6.407ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.804m	6.407ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.804m	6.407ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.689m	3.884ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	5.002m	7.160ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	19.389m	20.819ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.689m	3.884ms	1	1	100.00
		chip_sw_keymgr_key_derivation	10.534m	6.342ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.002m	4.506ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.757m	3.743ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	19.389m	20.819ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.689m	3.884ms	1	1	100.00
		chip_sw_keymgr_key_derivation	10.534m	6.342ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.002m	4.506ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.757m	3.743ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	5.002m	7.160ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	6.292m	5.821ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.570m	3.521ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.353m	3.330ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.207m	7.824ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.699m	6.429ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.021m	5.663ms	1	1	100.00
		chip_sw_lc_ctrl_transition	5.002m	7.160ms	1	1	100.00
		chip_prim_tl_access	3.166m	9.438ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	3.166m	9.438ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	16.809m	8.045ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	5.313m	8.060ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	16.510m	27.508ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.293m	7.666ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	6.304m	7.816ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	5.711m	6.556ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	17.301m	23.684ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	13.516m	17.362ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	7.519m	9.952ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	12.022m	13.156ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.311m	5.588ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	5.313m	8.060ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	5.119m	4.233ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	37.507m	40.404ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	5.490m	8.078ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	5.087m	5.336ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	19.354m	20.919ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	7.544m	6.088ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	13.253m	11.676ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	26.063m	28.657ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.104m	2.251ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	5.815m	5.708ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	3.873m	9.829ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	3.873m	9.829ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	13.253m	11.676ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	19.354m	20.919ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	5.311m	5.588ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.647m	4.574ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.463m	4.914ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.662m	4.782ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.851m	4.366ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	12.682m	11.211ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.522m	2.547ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	5.815m	5.708ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	14.010m	7.320ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.584m	4.671ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.196m	4.448ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.410m	2.970ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.757m	3.743ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.662m	4.782ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.662m	4.782ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	25.788m	20.000ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	14.006m	14.159ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.463m	4.914ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	5.223m	5.220ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.513m	6.873ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	4.679m	5.515ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	4.336m	11.435ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	8.460m	5.374ms	1	1	100.00
		chip_plic_all_irqs_10	4.110m	3.889ms	1	1	100.00
		chip_plic_all_irqs_20	5.846m	3.941ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.092m	3.397ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.347m	2.329ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	40.618m	14.921ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	6.298m	5.695ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.390m	2.924ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	2.963m	3.583ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.820m	3.546ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	5.002m	4.506ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.912m	4.651ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	5.225m	7.735ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	4.806m	5.940ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	5.302m	6.077ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	5.815m	5.708ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.002m	5.362ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	7.544m	6.088ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	18.035m	23.123ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.225m	2.882ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.441m	3.756ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	4.561m	4.235ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	18.035m	23.123ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	18.035m	23.123ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	34.061m	21.200ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	34.061m	21.200ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.328m	5.942ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	6.321m	18.721ms	1	1	100.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	1.888m	2.111ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.046m	2.465ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.022m	3.212ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.055m	3.577ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	16.888m	7.602ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.271h	31.404ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	26.877m	12.183ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.792m	2.938ms	1	1	100.00
V2		TOTAL			242	275	88.00
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.955m	2.942ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.522m	2.445ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.449h	71.739ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	6.315m	3.549ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	17.044m	11.599ms	1	1	100.00
		rom_e2e_jtag_debug_dev	15.415m	10.397ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.211m	11.442ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.656m	5.326ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.749m	4.055ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.694m	3.964ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	15.858s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.303m	5.030ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.254m	2.676ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	9.289m	4.937ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	19.063m	9.798ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.499m	2.586ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.648m	5.505ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	58.770s	1.820ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	4.587m	5.078ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.578m	6.777ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.024m	5.240ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	13.253m	11.676ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	17.044m	11.599ms	1	1	100.00
		rom_e2e_jtag_debug_dev	15.415m	10.397ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.211m	11.442ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	4.556m	4.486ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	5.815m	5.708ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.353h	38.159ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.353h	38.159ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.609m	3.955ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.183m	4.310ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	48.346m	19.381ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	2.646m	2.740ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	4.735m	4.262ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.149m	2.756ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.088m	3.000ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.945m	3.897ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	11.089s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	3.152m	3.168ms	1	1	100.00
		TOTAL			287	325	88.31

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.103599959858363038540379654091008560874335252597651938338541668249305631404881
    Line 630, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.14334271246524593743167184692594772951923137743821897973401725191631473488386
    Line 652, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.20658845858990272473375805071055385200248080937788071891335387394016769639443
    Line 626, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.44557475652137561414030953229818258350331780781399888544309615249895460447506
    Line 615, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.21668409265776282763420726627544838678917830596026157136851339351720503834980
    Line 774, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.111739041268999766525564001627237405888731266256894079902535338988864295399143
    Line 500, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.45404076739468809627092719434910649035156289757170990808527117127222980514648
    Line 492, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.77381195868137179048821698403581612505725423606675028841925333666578700395465
    Line 608, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.57276755126449518065051981218652236171797890473437014120808406659264301955067
    Line 660, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.20308423106478497789718215256969755991485963931863730660126477921789331443621
    Line 684, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.110218970222061688538318701711936627228570538550795548183680179678009165781611
    Line 610, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.95770032776333454122878080287428500209845605190270023602589384812743312041097
    Line 582, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.65621205157833281463598839409759034205204285705492622748834053955087019644841
    Line 687, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.96599438319657066355626837817831146870808918881656231527367743747153704046769
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.487s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.23869969500725889518982208702006250921645004063640006682764975610437319402148
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 5.614s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.32185916652367668397549675600191534163934742070763821919390964407222566705803
    Line 707, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.96908662496641807059919592729029221691528169967979902706644550035298055795280
    Line 832, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.8524148109266283858873479715809205343488225765498989166098493352226225439013
    Line 686, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.53635905118967761987700907010968099216803555628825815977031256626599969500390
    Line 701, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.16088975584498020508418308760837681038830993693767498485118178768992226704510
    Line 451, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2923.602778 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 2923.602778 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@92941) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.12303111182190796400887967645209066876815440922253189394038738274607892105662
Line 449, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4782.294212 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@92941) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4782.294212 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.36664045714547166166960733947042960414343115833372146918396266146708247648601
    Line 404, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3188.322342 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 3188.322342 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.29915037466605573385991022600052789049068298440395426686440726852391793458836
    Line 406, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3258.453450 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 3258.453450 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.63989702798078055784731568891268991493629742385889295764095106568988018682011
    Line 420, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2282.154119 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 2282.154119 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34349) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.21158924004258527173044271959197603591363479938477256278539925177602241756164
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 1983.771868 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34349) { a_addr: 'h106a0  a_data: 'hbf3a0e91  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h33  a_opcode: 'h4  a_user: 'h1b6b3  d_param: 'h0  d_source: 'h33  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1983.771868 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.68496990832469484345148470078785352140251768301258352595982241053396815553957
    Line 420, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2444.647524 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2444.647524 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.9039828560997173256892584101781732567368233302071483781351367765319676474747
    Line 413, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3204.624000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3204.624000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.6697785455415402745278425273473594568725990422552100342197284675930255545918
    Line 424, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3222.920000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3222.920000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.32795247734727263714755581784209309372153285921820526855453711791608517172883
    Line 462, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3549.115988 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3549.115988 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.86270757676754008099996370328650293711332930199611898245877853564327610444271
    Line 638, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.110564211986707690961093853485947563333326117291092367047442803725231771201464
    Line 779, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32247) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.112157388085740244920850816184373803773589968621985939606908079712167314417010
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2320.651424 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32247) { a_addr: 'h10610  a_data: 'hd9fb7788  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h34  a_opcode: 'h4  a_user: 'h1ba15  d_param: 'h0  d_source: 'h34  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2320.651424 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---