ADC_CTRL Simulation Results

Thursday April 24 2025 20:28:32 UTC

GitHub Revision: 0fa5019

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	11.720s	6.103ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.390s	974.595us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.820s	482.258us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	3.290s	2.835ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.050s	985.760us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.640s	493.939us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.820s	482.258us	1	1	100.00
		adc_ctrl_csr_aliasing	4.050s	985.760us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	9.123m	329.406ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	14.124m	493.347ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	14.452m	496.829ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	6.436m	336.926ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	34.310s	181.880ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	15.668m	606.553ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	14.346m	483.524ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	1.032m	163.265ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	4.220s	3.396ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	30.610s	33.992ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	33.570s	68.440ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	5.908m	218.976ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.860s	534.204us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.620s	358.942us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.110s	512.198us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.110s	512.198us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.390s	974.595us	1	1	100.00
		adc_ctrl_csr_rw	1.820s	482.258us	1	1	100.00
		adc_ctrl_csr_aliasing	4.050s	985.760us	1	1	100.00
		adc_ctrl_same_csr_outstanding	14.700s	4.841ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.390s	974.595us	1	1	100.00
		adc_ctrl_csr_rw	1.820s	482.258us	1	1	100.00
		adc_ctrl_csr_aliasing	4.050s	985.760us	1	1	100.00
		adc_ctrl_same_csr_outstanding	14.700s	4.841ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	8.690s	4.082ms	1	1	100.00
		adc_ctrl_tl_intg_err	3.630s	4.622ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	3.630s	4.622ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	8.530s	8.215ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00