AES/UNMASKED Simulation Results

Thursday April 24 2025 20:28:32 UTC

GitHub Revision: 0fa5019

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	88.208us	1	1	100.00
V1	smoke	aes_smoke	5.000s	119.306us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	93.532us	1	1	100.00
V1	csr_rw	aes_csr_rw	4.000s	77.294us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	594.868us	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	164.469us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	85.336us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	77.294us	1	1	100.00
		aes_csr_aliasing	5.000s	164.469us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	5.000s	119.306us	1	1	100.00
		aes_config_error	5.000s	129.160us	1	1	100.00
		aes_stress	5.000s	96.747us	1	1	100.00
V2	key_length	aes_smoke	5.000s	119.306us	1	1	100.00
		aes_config_error	5.000s	129.160us	1	1	100.00
		aes_stress	5.000s	96.747us	1	1	100.00
V2	back2back	aes_stress	5.000s	96.747us	1	1	100.00
		aes_b2b	6.000s	192.859us	1	1	100.00
V2	backpressure	aes_stress	5.000s	96.747us	1	1	100.00
V2	multi_message	aes_smoke	5.000s	119.306us	1	1	100.00
		aes_config_error	5.000s	129.160us	1	1	100.00
		aes_stress	5.000s	96.747us	1	1	100.00
		aes_alert_reset	6.000s	117.703us	1	1	100.00
V2	failure_test	aes_man_cfg_err	5.000s	64.313us	1	1	100.00
		aes_config_error	5.000s	129.160us	1	1	100.00
		aes_alert_reset	6.000s	117.703us	1	1	100.00
V2	trigger_clear_test	aes_clear	7.000s	464.270us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	285.520us	1	1	100.00
V2	reset_recovery	aes_alert_reset	6.000s	117.703us	1	1	100.00
V2	stress	aes_stress	5.000s	96.747us	1	1	100.00
V2	sideload	aes_stress	5.000s	96.747us	1	1	100.00
		aes_sideload	4.000s	120.701us	1	1	100.00
V2	deinitialization	aes_deinit	5.000s	173.146us	1	1	100.00
V2	stress_all	aes_stress_all	8.000s	486.489us	1	1	100.00
V2	alert_test	aes_alert_test	5.000s	59.748us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	169.459us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	169.459us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	93.532us	1	1	100.00
		aes_csr_rw	4.000s	77.294us	1	1	100.00
		aes_csr_aliasing	5.000s	164.469us	1	1	100.00
		aes_same_csr_outstanding	4.000s	96.409us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	93.532us	1	1	100.00
		aes_csr_rw	4.000s	77.294us	1	1	100.00
		aes_csr_aliasing	5.000s	164.469us	1	1	100.00
		aes_same_csr_outstanding	4.000s	96.409us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	5.000s	565.431us	1	1	100.00
V2S	fault_inject	aes_fi	4.000s	37.317us	0	1	0.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	4.000s	63.622us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	91.325us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	91.325us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	91.325us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	91.325us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	134.152us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	530.860us	1	1	100.00
		aes_tl_intg_err	5.000s	169.134us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	169.134us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	6.000s	117.703us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	91.325us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	5.000s	119.306us	1	1	100.00
		aes_stress	5.000s	96.747us	1	1	100.00
		aes_alert_reset	6.000s	117.703us	1	1	100.00
		aes_core_fi	5.000s	107.464us	1	1	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	91.325us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	66.956us	1	1	100.00
		aes_stress	5.000s	96.747us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	5.000s	96.747us	1	1	100.00
		aes_sideload	4.000s	120.701us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	66.956us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	66.956us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	66.956us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	66.956us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	66.956us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	5.000s	96.747us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	5.000s	96.747us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	4.000s	37.317us	0	1	0.00
V2S	sec_cm_main_fsm_redun	aes_fi	4.000s	37.317us	0	1	0.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	4.000s	63.622us	1	1	100.00
		aes_ctr_fi	4.000s	156.070us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	4.000s	37.317us	0	1	0.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	4.000s	37.317us	0	1	0.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	4.000s	63.622us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	4.000s	63.622us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	4.000s	37.317us	0	1	0.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	4.000s	37.317us	0	1	0.00
		aes_control_fi			0	1	0.00
		aes_ctr_fi	4.000s	156.070us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	4.000s	37.317us	0	1	0.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	4.000s	63.622us	1	1	100.00
		aes_ctr_fi	4.000s	156.070us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	6.000s	117.703us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	4.000s	37.317us	0	1	0.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	4.000s	63.622us	1	1	100.00
		aes_ctr_fi	4.000s	156.070us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	4.000s	37.317us	0	1	0.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	4.000s	63.622us	1	1	100.00
		aes_ctr_fi	4.000s	156.070us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	4.000s	37.317us	0	1	0.00
		aes_control_fi			0	1	0.00
		aes_ctr_fi	4.000s	156.070us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	4.000s	37.317us	0	1	0.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	4.000s	63.622us	1	1	100.00
V2S		TOTAL			9	11	81.82
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	17.000s	1.632ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			29	32	90.62

Failure Buckets

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

  • Test aes_fi has 1 failures.

    • 0.aes_fi.73349243304059550249210189781698894881023392354221102064343425359356668534221
      Line 996, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_fi/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 37316674 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 37205563 PS)
              ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                         |
        xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 37316674 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 37205563 PS)
        UVM_ERROR @  37316674 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
      

• Job timed out after * minutes has 1 failures:

  • Test aes_control_fi has 1 failures.

    • 0.aes_control_fi.4320352306031359374172433812984856396861219460642522075515279691271595203178
      Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_control_fi/latest/run.log

        Job timed out after 1 minutes
      

• UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:

  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.53533342691590883787189428022201047741844237250889956912383504922848370767205
      Line 1383, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1631638000 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
        UVM_INFO @ 1631638000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---