0fa5019| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | entropy_src_smoke | 5.000s | 55.255us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | entropy_src_csr_hw_reset | 4.000s | 159.889us | 1 | 1 | 100.00 |
| V1 | csr_rw | entropy_src_csr_rw | 5.000s | 230.035us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | entropy_src_csr_bit_bash | 11.000s | 1.559ms | 1 | 1 | 100.00 |
| V1 | csr_aliasing | entropy_src_csr_aliasing | 7.000s | 1.835ms | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | entropy_src_csr_mem_rw_with_rand_reset | 4.000s | 32.826us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | entropy_src_csr_rw | 5.000s | 230.035us | 1 | 1 | 100.00 |
| entropy_src_csr_aliasing | 7.000s | 1.835ms | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 6 | 100.00 | |||
| V2 | firmware | entropy_src_smoke | 5.000s | 55.255us | 1 | 1 | 100.00 |
| entropy_src_rng | 9.000s | 178.417us | 0 | 1 | 0.00 | ||
| entropy_src_fw_ov | 8.000s | 215.609us | 0 | 1 | 0.00 | ||
| V2 | firmware_mode | entropy_src_fw_ov | 8.000s | 215.609us | 0 | 1 | 0.00 |
| V2 | rng_mode | entropy_src_rng | 9.000s | 178.417us | 0 | 1 | 0.00 |
| V2 | rng_max_rate | entropy_src_rng_max_rate | 4.000s | 25.511us | 0 | 1 | 0.00 |
| V2 | health_checks | entropy_src_rng | 9.000s | 178.417us | 0 | 1 | 0.00 |
| V2 | conditioning | entropy_src_rng | 9.000s | 178.417us | 0 | 1 | 0.00 |
| V2 | interrupts | entropy_src_rng | 9.000s | 178.417us | 0 | 1 | 0.00 |
| entropy_src_intr | 9.000s | 1.119ms | 1 | 1 | 100.00 | ||
| V2 | alerts | entropy_src_rng | 9.000s | 178.417us | 0 | 1 | 0.00 |
| entropy_src_functional_alerts | 5.000s | 244.781us | 1 | 1 | 100.00 | ||
| V2 | stress_all | entropy_src_stress_all | 29.000s | 11.057ms | 1 | 1 | 100.00 |
| V2 | functional_errors | entropy_src_functional_errors | 5.000s | 105.429us | 1 | 1 | 100.00 |
| V2 | firmware_ov_read_contiguous_data | entropy_src_fw_ov_contiguous | 5.000s | 116.468us | 1 | 1 | 100.00 |
| V2 | intr_test | entropy_src_intr_test | 5.000s | 28.808us | 1 | 1 | 100.00 |
| V2 | alert_test | entropy_src_alert_test | 4.000s | 27.228us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | entropy_src_tl_errors | 6.000s | 121.751us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | entropy_src_tl_errors | 6.000s | 121.751us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | entropy_src_csr_hw_reset | 4.000s | 159.889us | 1 | 1 | 100.00 |
| entropy_src_csr_rw | 5.000s | 230.035us | 1 | 1 | 100.00 | ||
| entropy_src_csr_aliasing | 7.000s | 1.835ms | 1 | 1 | 100.00 | ||
| entropy_src_same_csr_outstanding | 4.000s | 70.842us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | entropy_src_csr_hw_reset | 4.000s | 159.889us | 1 | 1 | 100.00 |
| entropy_src_csr_rw | 5.000s | 230.035us | 1 | 1 | 100.00 | ||
| entropy_src_csr_aliasing | 7.000s | 1.835ms | 1 | 1 | 100.00 | ||
| entropy_src_same_csr_outstanding | 4.000s | 70.842us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 9 | 12 | 75.00 | |||
| V2S | tl_intg_err | entropy_src_sec_cm | 5.000s | 165.049us | 1 | 1 | 100.00 |
| entropy_src_tl_intg_err | 5.000s | 400.056us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_config_regwen | entropy_src_rng | 9.000s | 178.417us | 0 | 1 | 0.00 |
| entropy_src_cfg_regwen | 4.000s | 34.858us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_config_mubi | entropy_src_rng | 9.000s | 178.417us | 0 | 1 | 0.00 |
| V2S | sec_cm_config_redun | entropy_src_rng | 9.000s | 178.417us | 0 | 1 | 0.00 |
| V2S | sec_cm_intersig_mubi | entropy_src_rng | 9.000s | 178.417us | 0 | 1 | 0.00 |
| entropy_src_fw_ov | 8.000s | 215.609us | 0 | 1 | 0.00 | ||
| V2S | sec_cm_main_sm_fsm_sparse | entropy_src_functional_errors | 5.000s | 105.429us | 1 | 1 | 100.00 |
| entropy_src_sec_cm | 5.000s | 165.049us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_ack_sm_fsm_sparse | entropy_src_functional_errors | 5.000s | 105.429us | 1 | 1 | 100.00 |
| entropy_src_sec_cm | 5.000s | 165.049us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_rng_bkgn_chk | entropy_src_rng | 9.000s | 178.417us | 0 | 1 | 0.00 |
| V2S | sec_cm_fifo_ctr_redun | entropy_src_functional_errors | 5.000s | 105.429us | 1 | 1 | 100.00 |
| entropy_src_sec_cm | 5.000s | 165.049us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_ctr_redun | entropy_src_functional_errors | 5.000s | 105.429us | 1 | 1 | 100.00 |
| entropy_src_sec_cm | 5.000s | 165.049us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_ctr_local_esc | entropy_src_functional_errors | 5.000s | 105.429us | 1 | 1 | 100.00 |
| V2S | sec_cm_esfinal_rdata_bus_consistency | entropy_src_functional_alerts | 5.000s | 244.781us | 1 | 1 | 100.00 |
| V2S | sec_cm_tile_link_bus_integrity | entropy_src_tl_intg_err | 5.000s | 400.056us | 1 | 1 | 100.00 |
| V2S | TOTAL | 3 | 3 | 100.00 | |||
| V3 | external_health_tests | entropy_src_rng_with_xht_rsps | 8.000s | 334.461us | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 18 | 22 | 81.82 |
UVM_ERROR (entropy_src_scoreboard.sv:2073) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: entropy_src_reg_block.recov_alert_sts has 2 failures:
Test entropy_src_rng has 1 failures.
0.entropy_src_rng.107269176973905957510091215068338368563845932578727089021505075943423891326588
Line 312, in log /nightly/runs/scratch/master/entropy_src-sim-xcelium/0.entropy_src_rng/latest/run.log
UVM_ERROR @ 178416562 ps: (entropy_src_scoreboard.sv:2073) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 131072 [0x20000]) reg name: entropy_src_reg_block.recov_alert_sts
UVM_INFO @ 178416562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test entropy_src_rng_with_xht_rsps has 1 failures.
0.entropy_src_rng_with_xht_rsps.49809829338424433028036437287898888857420123799413641588593619961374323513113
Line 259, in log /nightly/runs/scratch/master/entropy_src-sim-xcelium/0.entropy_src_rng_with_xht_rsps/latest/run.log
UVM_ERROR @ 334461288 ps: (entropy_src_scoreboard.sv:2073) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 131072 [0x20000]) reg name: entropy_src_reg_block.recov_alert_sts
UVM_INFO @ 334461288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/runs/scratch/master/entropy_src-sim-xcelium/default/src/lowrisc_fpv_entropy_src_csr_assert_*/entropy_src_csr_assert_fpv.sv,294): Assertion conf_rd_A has failed has 2 failures:
Test entropy_src_rng_max_rate has 1 failures.
0.entropy_src_rng_max_rate.109267817779102450919134805275813180216841456001574172698819251311093890031938
Line 203, in log /nightly/runs/scratch/master/entropy_src-sim-xcelium/0.entropy_src_rng_max_rate/latest/run.log
xmsim: *E,ASRTST (/nightly/runs/scratch/master/entropy_src-sim-xcelium/default/src/lowrisc_fpv_entropy_src_csr_assert_0/entropy_src_csr_assert_fpv.sv,294): (time 25510537 PS) Assertion tb.dut.entropy_src_csr_assert.conf_rd_A has failed
UVM_ERROR @ 25510537 ps: (entropy_src_csr_assert_fpv.sv:294) [ASSERT FAILED] conf_rd_A
UVM_INFO @ 25510537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test entropy_src_fw_ov has 1 failures.
0.entropy_src_fw_ov.27817910262968782245050633962927121591459091654802523064896465600374632536244
Line 255, in log /nightly/runs/scratch/master/entropy_src-sim-xcelium/0.entropy_src_fw_ov/latest/run.log
xmsim: *E,ASRTST (/nightly/runs/scratch/master/entropy_src-sim-xcelium/default/src/lowrisc_fpv_entropy_src_csr_assert_0/entropy_src_csr_assert_fpv.sv,294): (time 215608626 PS) Assertion tb.dut.entropy_src_csr_assert.conf_rd_A has failed
UVM_ERROR @ 215608626 ps: (entropy_src_csr_assert_fpv.sv:294) [ASSERT FAILED] conf_rd_A
UVM_INFO @ 215608626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---