HMAC Simulation Results

Thursday April 24 2025 20:28:32 UTC

GitHub Revision: 0fa5019

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 9.880s 3.543ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.630s 63.352us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.800s 32.140us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 13.580s 12.053ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 5.540s 1.237ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.540s 179.230us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.800s 32.140us 1 1 100.00
hmac_csr_aliasing 5.540s 1.237ms 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 35.750s 889.381us 1 1 100.00
V2 back_pressure hmac_back_pressure 48.970s 4.266ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.398m 34.355ms 1 1 100.00
hmac_test_sha384_vectors 7.115m 53.839ms 1 1 100.00
hmac_test_sha512_vectors 4.434m 8.531ms 1 1 100.00
hmac_test_hmac256_vectors 8.340s 890.734us 1 1 100.00
hmac_test_hmac384_vectors 10.860s 1.256ms 1 1 100.00
hmac_test_hmac512_vectors 12.590s 381.358us 1 1 100.00
V2 burst_wr hmac_burst_wr 18.980s 462.982us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 14.631m 27.683ms 1 1 100.00
V2 error hmac_error 34.520s 3.250ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 51.950s 1.667ms 1 1 100.00
V2 save_and_restore hmac_smoke 9.880s 3.543ms 1 1 100.00
hmac_long_msg 35.750s 889.381us 1 1 100.00
hmac_back_pressure 48.970s 4.266ms 1 1 100.00
hmac_datapath_stress 14.631m 27.683ms 1 1 100.00
hmac_burst_wr 18.980s 462.982us 1 1 100.00
hmac_stress_all 19.760s 6.441ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 9.880s 3.543ms 1 1 100.00
hmac_long_msg 35.750s 889.381us 1 1 100.00
hmac_back_pressure 48.970s 4.266ms 1 1 100.00
hmac_datapath_stress 14.631m 27.683ms 1 1 100.00
hmac_wipe_secret 51.950s 1.667ms 1 1 100.00
hmac_test_sha256_vectors 3.398m 34.355ms 1 1 100.00
hmac_test_sha384_vectors 7.115m 53.839ms 1 1 100.00
hmac_test_sha512_vectors 4.434m 8.531ms 1 1 100.00
hmac_test_hmac256_vectors 8.340s 890.734us 1 1 100.00
hmac_test_hmac384_vectors 10.860s 1.256ms 1 1 100.00
hmac_test_hmac512_vectors 12.590s 381.358us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 9.880s 3.543ms 1 1 100.00
hmac_long_msg 35.750s 889.381us 1 1 100.00
hmac_back_pressure 48.970s 4.266ms 1 1 100.00
hmac_datapath_stress 14.631m 27.683ms 1 1 100.00
hmac_burst_wr 18.980s 462.982us 1 1 100.00
hmac_error 34.520s 3.250ms 1 1 100.00
hmac_wipe_secret 51.950s 1.667ms 1 1 100.00
hmac_test_sha256_vectors 3.398m 34.355ms 1 1 100.00
hmac_test_sha384_vectors 7.115m 53.839ms 1 1 100.00
hmac_test_sha512_vectors 4.434m 8.531ms 1 1 100.00
hmac_test_hmac256_vectors 8.340s 890.734us 1 1 100.00
hmac_test_hmac384_vectors 10.860s 1.256ms 1 1 100.00
hmac_test_hmac512_vectors 12.590s 381.358us 1 1 100.00
hmac_stress_all 19.760s 6.441ms 1 1 100.00
V2 stress_all hmac_stress_all 19.760s 6.441ms 1 1 100.00
V2 alert_test hmac_alert_test 1.510s 17.794us 1 1 100.00
V2 intr_test hmac_intr_test 1.790s 20.952us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.670s 239.977us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.670s 239.977us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.630s 63.352us 1 1 100.00
hmac_csr_rw 1.800s 32.140us 1 1 100.00
hmac_csr_aliasing 5.540s 1.237ms 1 1 100.00
hmac_same_csr_outstanding 2.450s 104.505us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.630s 63.352us 1 1 100.00
hmac_csr_rw 1.800s 32.140us 1 1 100.00
hmac_csr_aliasing 5.540s 1.237ms 1 1 100.00
hmac_same_csr_outstanding 2.450s 104.505us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.520s 32.152us 1 1 100.00
hmac_tl_intg_err 2.210s 53.300us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.210s 53.300us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 9.880s 3.543ms 1 1 100.00
V3 stress_reset hmac_stress_reset 3.140s 135.983us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.264m 9.133ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.970s 52.820us 1 1 100.00
TOTAL 28 28 100.00