I2C Simulation Results

Thursday April 24 2025 20:28:32 UTC

GitHub Revision: 0fa5019

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	14.670s	2.421ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	10.540s	4.716ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.410s	19.317us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.560s	31.388us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.940s	972.870us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.080s	108.736us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.760s	94.839us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.560s	31.388us	1	1	100.00
		i2c_csr_aliasing	2.080s	108.736us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	5.950s	248.175us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	3.910m	54.076ms	1	1	100.00
V2	host_maxperf	i2c_host_perf	43.770s	18.698ms	1	1	100.00
V2	host_override	i2c_host_override	1.690s	26.701us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	38.910s	3.090ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.961m	2.598ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.790s	110.356us	1	1	100.00
		i2c_host_fifo_fmt_empty	16.880s	468.860us	1	1	100.00
		i2c_host_fifo_reset_rx	7.940s	202.993us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.718m	10.331ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	6.690s	1.642ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	4.050s	262.925us	1	1	100.00
V2	target_glitch	i2c_target_glitch	8.920s	2.840ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	3.193m	35.397ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	5.950s	927.942us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	51.450s	7.706ms	1	1	100.00
		i2c_target_intr_smoke	3.990s	846.800us	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.480s	482.665us	1	1	100.00
		i2c_target_fifo_reset_tx	1.990s	1.166ms	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	26.300s	45.693ms	1	1	100.00
		i2c_target_stress_rd	51.450s	7.706ms	1	1	100.00
		i2c_target_intr_stress_wr	1.007m	15.979ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	6.060s	2.772ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	6.930s	1.791ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.230s	3.159ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	6.170s	10.046ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.800s	1.528ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.170s	248.589us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	43.770s	18.698ms	1	1	100.00
		i2c_host_perf_precise	7.770s	2.933ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	6.690s	1.642ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.800s	105.854us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.940s	4.920ms	1	1	100.00
		i2c_target_nack_acqfull_addr	3.130s	646.634us	1	1	100.00
		i2c_target_nack_txstretch	2.130s	189.420us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	7.630s	413.826us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.550s	823.766us	1	1	100.00
V2	alert_test	i2c_alert_test	1.610s	38.425us	1	1	100.00
V2	intr_test	i2c_intr_test	1.500s	43.363us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.020s	191.842us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.020s	191.842us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.410s	19.317us	1	1	100.00
		i2c_csr_rw	1.560s	31.388us	1	1	100.00
		i2c_csr_aliasing	2.080s	108.736us	1	1	100.00
		i2c_same_csr_outstanding	2.090s	58.568us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.410s	19.317us	1	1	100.00
		i2c_csr_rw	1.560s	31.388us	1	1	100.00
		i2c_csr_aliasing	2.080s	108.736us	1	1	100.00
		i2c_same_csr_outstanding	2.090s	58.568us	1	1	100.00
V2		TOTAL			37	38	97.37
V2S	tl_intg_err	i2c_tl_intg_err	1.990s	68.863us	1	1	100.00
		i2c_sec_cm	1.810s	44.790us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.990s	68.863us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	32.700s	3.379ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.620s	44.008us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	4.710s	260.877us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			46	50	92.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.112151208345618553675135274603916276572215729278691174328094915632131745704795
      Line 88, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3378533470 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3378533470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.57052002017995156007996119108934869785521717927323435083011392413176817221369
      Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 260877058 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 260877058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.37015434735045408622466360720593580173770976448003074632165163552819191088293
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @  44007887 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
        UVM_INFO @  44007887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.39028683315726528930047696255235206450016504270519840016936924784766276559208
      Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10046334619 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10046334619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---