KEYMGR Simulation Results

Thursday April 24 2025 20:28:32 UTC

GitHub Revision: 0fa5019

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.900s	49.501us	1	1	100.00
V1	random	keymgr_random	5.140s	164.784us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.890s	15.557us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.890s	15.222us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	9.120s	1.095ms	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	3.940s	925.145us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.580s	28.167us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.890s	15.222us	1	1	100.00
		keymgr_csr_aliasing	3.940s	925.145us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	3.520s	97.738us	1	1	100.00
V2	sideload	keymgr_sideload	5.220s	325.509us	1	1	100.00
		keymgr_sideload_kmac	3.570s	89.833us	1	1	100.00
		keymgr_sideload_aes	5.440s	583.910us	1	1	100.00
		keymgr_sideload_otbn	29.980s	5.308ms	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.770s	128.808us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	5.280s	420.926us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.530s	187.181us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	4.670s	665.745us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	2.700s	33.933us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	6.270s	1.130ms	1	1	100.00
V2	stress_all	keymgr_stress_all	20.550s	1.340ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.700s	36.212us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.810s	14.708us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.520s	109.063us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.520s	109.063us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.890s	15.557us	1	1	100.00
		keymgr_csr_rw	1.890s	15.222us	1	1	100.00
		keymgr_csr_aliasing	3.940s	925.145us	1	1	100.00
		keymgr_same_csr_outstanding	2.410s	84.980us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.890s	15.557us	1	1	100.00
		keymgr_csr_rw	1.890s	15.222us	1	1	100.00
		keymgr_csr_aliasing	3.940s	925.145us	1	1	100.00
		keymgr_same_csr_outstanding	2.410s	84.980us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	8.010s	3.620ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	8.010s	3.620ms	1	1	100.00
		keymgr_tl_intg_err	4.450s	138.746us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	3.250s	108.454us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	3.250s	108.454us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	3.250s	108.454us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	3.250s	108.454us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	2.530s	116.140us	0	1	0.00
V2S	prim_count_check	keymgr_sec_cm	8.010s	3.620ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	8.010s	3.620ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	4.450s	138.746us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	3.250s	108.454us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	3.520s	97.738us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	5.140s	164.784us	1	1	100.00
		keymgr_csr_rw	1.890s	15.222us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	5.140s	164.784us	1	1	100.00
		keymgr_csr_rw	1.890s	15.222us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	5.140s	164.784us	1	1	100.00
		keymgr_csr_rw	1.890s	15.222us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	5.280s	420.926us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	2.700s	33.933us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	2.700s	33.933us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	5.140s	164.784us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	3.080s	188.882us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	8.010s	3.620ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	8.010s	3.620ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	8.010s	3.620ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	3.630s	77.876us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	5.280s	420.926us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	8.010s	3.620ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	8.010s	3.620ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	8.010s	3.620ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	3.630s	77.876us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	3.630s	77.876us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	8.010s	3.620ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	3.630s	77.876us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	8.010s	3.620ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	3.630s	77.876us	1	1	100.00
V2S		TOTAL			5	6	83.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	2.800s	824.655us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			28	30	93.33

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 0.keymgr_stress_all_with_rand_reset.2479077783116594441502261249782662501684290629809623307188861454312061791706
      Line 193, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 824655256 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 824655256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test keymgr_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.keymgr_shadow_reg_errors_with_csr_rw.2130745764047970249852185960870365561723728055337863995215152227727375735073
      Line 79, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[7] & 'hffffffff)))'
        UVM_ERROR @ 116140488 ps: (keymgr_csr_assert_fpv.sv:401) [ASSERT FAILED] sealing_sw_binding_2_rd_A
        UVM_INFO @ 116140488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---