KMAC/UNMASKED Simulation Results

Thursday April 24 2025 20:28:32 UTC

GitHub Revision: 0fa5019

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	29.770s	8.926ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.900s	26.616us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.760s	28.535us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.680s	2.078ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	5.940s	502.995us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.610s	74.464us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.760s	28.535us	1	1	100.00
		kmac_csr_aliasing	5.940s	502.995us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.510s	16.487us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.030s	99.208us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	39.979m	454.345ms	1	1	100.00
V2	burst_write	kmac_burst_write	2.251m	77.897ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	31.730s	7.415ms	1	1	100.00
		kmac_test_vectors_sha3_256	17.209m	34.915ms	1	1	100.00
		kmac_test_vectors_sha3_384	30.400s	4.543ms	1	1	100.00
		kmac_test_vectors_sha3_512	11.939m	35.006ms	1	1	100.00
		kmac_test_vectors_shake_128	20.426m	20.402ms	1	1	100.00
		kmac_test_vectors_shake_256	1.335m	4.799ms	1	1	100.00
		kmac_test_vectors_kmac	2.390s	41.600us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.500s	35.772us	1	1	100.00
V2	sideload	kmac_sideload	1.276m	18.803ms	1	1	100.00
V2	app	kmac_app	2.675m	27.375ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.959m	7.712ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.181m	46.256ms	1	1	100.00
V2	error	kmac_error	1.010m	4.327ms	1	1	100.00
V2	key_error	kmac_key_error	9.230s	11.402ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	1.445m	10.011ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	8.740s	1.067ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	30.190s	1.085ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	33.030s	2.238ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	9.230s	909.841us	1	1	100.00
V2	stress_all	kmac_stress_all	23.021m	73.828ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.990s	14.123us	1	1	100.00
V2	alert_test	kmac_alert_test	1.950s	41.274us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.020s	440.936us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.020s	440.936us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.900s	26.616us	1	1	100.00
		kmac_csr_rw	1.760s	28.535us	1	1	100.00
		kmac_csr_aliasing	5.940s	502.995us	1	1	100.00
		kmac_same_csr_outstanding	1.980s	49.496us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.900s	26.616us	1	1	100.00
		kmac_csr_rw	1.760s	28.535us	1	1	100.00
		kmac_csr_aliasing	5.940s	502.995us	1	1	100.00
		kmac_same_csr_outstanding	1.980s	49.496us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.070s	161.424us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.070s	161.424us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.070s	161.424us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.070s	161.424us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.680s	15.620us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	27.020s	4.774ms	1	1	100.00
		kmac_tl_intg_err	4.090s	763.610us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.090s	763.610us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	9.230s	909.841us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	29.770s	8.926ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.276m	18.803ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.070s	161.424us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	27.020s	4.774ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	27.020s	4.774ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	27.020s	4.774ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	29.770s	8.926ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	9.230s	909.841us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	27.020s	4.774ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.121m	4.125ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	29.770s	8.926ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.746m	19.283ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.53146021953240489697536690371615220988622462074241516917930943023388572869422
      Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10010897227 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa486e000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
        UVM_INFO @ 10010897227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.21052647788003292168078161624683605658533570884449684407454053454193919253310
      Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffff03ff) == (exp_vals[4] & 'hffff03ff)))'
        UVM_ERROR @  15620355 ps: (kmac_csr_assert_fpv.sv:487) [ASSERT FAILED] entropy_period_rd_A
        UVM_INFO @  15620355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---