OTBN Simulation Results

Thursday April 24 2025 20:28:32 UTC

GitHub Revision: 0fa5019

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	16.000s	46.413us	1	1	100.00
V1	single_binary	otbn_single	10.000s	30.116us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	11.000s	41.294us	1	1	100.00
V1	csr_rw	otbn_csr_rw	7.000s	30.995us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	23.709us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	8.000s	15.724us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	8.000s	67.375us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	30.995us	1	1	100.00
		otbn_csr_aliasing	8.000s	15.724us	1	1	100.00
V1	mem_walk	otbn_mem_walk	32.000s	6.593ms	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	17.000s	472.443us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	18.000s	64.318us	1	1	100.00
V2	multi_error	otbn_multi_err	50.000s	292.033us	1	1	100.00
V2	back_to_back	otbn_multi	9.917m	3.709ms	1	1	100.00
V2	stress_all	otbn_stress_all	19.000s	342.153us	1	1	100.00
V2	lc_escalation	otbn_escalate	9.000s	45.913us	0	1	0.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	27.375us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	9.000s	48.162us	1	1	100.00
V2	alert_test	otbn_alert_test	6.000s	46.860us	1	1	100.00
V2	intr_test	otbn_intr_test	8.000s	44.316us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	42.000s	188.072us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	42.000s	188.072us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	11.000s	41.294us	1	1	100.00
		otbn_csr_rw	7.000s	30.995us	1	1	100.00
		otbn_csr_aliasing	8.000s	15.724us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	26.585us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	11.000s	41.294us	1	1	100.00
		otbn_csr_rw	7.000s	30.995us	1	1	100.00
		otbn_csr_aliasing	8.000s	15.724us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	26.585us	1	1	100.00
V2		TOTAL			10	11	90.91
V2S	mem_integrity	otbn_imem_err	10.000s	20.663us	1	1	100.00
		otbn_dmem_err	10.000s	33.423us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	14.000s	59.281us	1	1	100.00
		otbn_controller_ispr_rdata_err	10.000s	28.261us	1	1	100.00
		otbn_mac_bignum_acc_err	8.000s	472.888us	1	1	100.00
		otbn_urnd_err	7.000s	28.437us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	18.507us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	7.000s	34.687us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	10.000s	39.170us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	1.950m	726.758us	1	1	100.00
		otbn_tl_intg_err	1.167m	374.317us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	57.000s	199.966us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	1.950m	726.758us	1	1	100.00
V2S	prim_count_check	otbn_sec_cm	1.950m	726.758us	1	1	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	16.000s	46.413us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	10.000s	33.423us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	10.000s	20.663us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	1.167m	374.317us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	9.000s	45.913us	0	1	0.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	10.000s	20.663us	1	1	100.00
		otbn_dmem_err	10.000s	33.423us	1	1	100.00
		otbn_zero_state_err_urnd	9.000s	27.375us	1	1	100.00
		otbn_illegal_mem_acc	9.000s	18.507us	1	1	100.00
		otbn_sec_cm	1.950m	726.758us	1	1	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	1.950m	726.758us	1	1	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	10.000s	30.116us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	10.000s	20.663us	1	1	100.00
		otbn_dmem_err	10.000s	33.423us	1	1	100.00
		otbn_zero_state_err_urnd	9.000s	27.375us	1	1	100.00
		otbn_illegal_mem_acc	9.000s	18.507us	1	1	100.00
		otbn_sec_cm	1.950m	726.758us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	1.950m	726.758us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	9.000s	45.913us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	10.000s	20.663us	1	1	100.00
		otbn_dmem_err	10.000s	33.423us	1	1	100.00
		otbn_zero_state_err_urnd	9.000s	27.375us	1	1	100.00
		otbn_illegal_mem_acc	9.000s	18.507us	1	1	100.00
		otbn_sec_cm	1.950m	726.758us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	1.950m	726.758us	1	1	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	10.000s	30.116us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	8.000s	13.302us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	11.963us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	25.000s	218.017us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	25.000s	218.017us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	8.000s	42.382us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	1.950m	726.758us	1	1	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	1.950m	726.758us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	11.000s	72.818us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	1.950m	726.758us	1	1	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	1.950m	726.758us	1	1	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	9.000s	20.227us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	9.000s	20.227us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	6.000s	65.553us	1	1	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	10.000s	30.116us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	10.000s	30.116us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	10.000s	30.116us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	9.917m	3.709ms	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	10.000s	30.116us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	10.000s	30.116us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	10.000s	50.733us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	10.000s	30.116us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	1.950m	726.758us	1	1	100.00
V2S		TOTAL			20	20	100.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	4.733m	6.296ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			40	41	97.56

Failure Buckets

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:
  • Test otbn_escalate has 1 failures.

    • 0.otbn_escalate.4930771643679283534943343044792886437082819017914114378116459565554211914409
      Line 114, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_escalate/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 45913022 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @  45913022 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @  45913022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---