PATTGEN Simulation Results

Thursday April 24 2025 20:28:32 UTC

GitHub Revision: `0fa5019`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	13.000s	45.663us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	4.000s	25.945us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	4.000s	15.366us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	6.000s	250.945us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	4.000s	13.935us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	86.722us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	4.000s	15.366us	1	1	100.00
		pattgen_csr_aliasing	4.000s	13.935us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	23.567m	600.000ms	0	1	0.00
V2	cnt_rollover	cnt_rollover	44.000s	21.948ms	1	1	100.00
V2	error	pattgen_error	11.000s	141.515us	1	1	100.00
V2	stress_all	pattgen_stress_all	9.600m	23.371ms	0	1	0.00
V2	alert_test	pattgen_alert_test	4.000s	51.828us	1	1	100.00
V2	intr_test	pattgen_intr_test	4.000s	12.867us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	262.720us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	262.720us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	4.000s	25.945us	1	1	100.00
		pattgen_csr_rw	4.000s	15.366us	1	1	100.00
		pattgen_csr_aliasing	4.000s	13.935us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	79.227us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	4.000s	25.945us	1	1	100.00
		pattgen_csr_rw	4.000s	15.366us	1	1	100.00
		pattgen_csr_aliasing	4.000s	13.935us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	79.227us	1	1	100.00
V2		TOTAL			6	8	75.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	202.186us	1	1	100.00
		pattgen_sec_cm	6.000s	232.193us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	202.186us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	18.000s	2.180ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	7.000s	46.677us	1	1	100.00
		TOTAL			15	18	83.33

Failure Buckets

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test pattgen_perf has 1 failures.
  - 0.pattgen_perf.14810757185597039050964177713530400241211162806480205298555370402000059855767
    Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_vseq.sv:929) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test pattgen_stress_all_with_rand_reset has 1 failures.

0.pattgen_stress_all_with_rand_reset.9223975836832671589132787150323722832206674416230122251431951115689766577742
Line 185, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1590008868 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1590017829 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1590017829 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 2/5
  UVM_INFO @ 1590112427 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:
- Test pattgen_stress_all has 1 failures.
  - 0.pattgen_stress_all.75820157268544883033263133187954095054797485799738478344928862496562789898177
    Line 150, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log
```
  UVM_ERROR @ 23371231443 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
  ------------------------------------
  Name      Type          Size  Value
  ------------------------------------
  exp_item  pattgen_item  -     @28188
```