SPI_DEVICE/1R1W Simulation Results

Thursday April 24 2025 20:28:32 UTC

GitHub Revision: 0fa5019

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	47.150s	23.731ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.830s	232.628us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.560s	65.826us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	9.720s	1.222ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	5.970s	212.769us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.270s	176.621us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.560s	65.826us	1	1	100.00
		spi_device_csr_aliasing	5.970s	212.769us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.480s	22.819us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.190s	119.566us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.840s	28.938us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.640s	1.222us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	2.040s	1.762us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.310s	194.598us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.310s	194.598us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	5.850s	1.610ms	1	1	100.00
		spi_device_tpm_sts_read	1.750s	78.416us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	12.130s	3.017ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	2.650s	33.128us	1	1	100.00
		spi_device_flash_all	2.886m	128.679ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	14.270s	4.655ms	1	1	100.00
		spi_device_flash_all	2.886m	128.679ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	14.270s	4.655ms	1	1	100.00
		spi_device_flash_all	2.886m	128.679ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	2.886m	128.679ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	4.230s	205.839us	1	1	100.00
		spi_device_flash_all	2.886m	128.679ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	4.230s	205.839us	1	1	100.00
		spi_device_flash_all	2.886m	128.679ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	4.230s	205.839us	1	1	100.00
		spi_device_flash_all	2.886m	128.679ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	4.230s	205.839us	1	1	100.00
		spi_device_flash_all	2.886m	128.679ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	4.230s	205.839us	1	1	100.00
		spi_device_flash_all	2.886m	128.679ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	7.370s	4.043ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	8.570s	1.582ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	8.570s	1.582ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	8.570s	1.582ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	4.530s	790.723us	1	1	100.00
		spi_device_read_buffer_direct	6.800s	3.869ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	8.570s	1.582ms	1	1	100.00
		spi_device_flash_all	2.886m	128.679ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	2.886m	128.679ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	2.886m	128.679ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.990s	1.228ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.990s	1.228ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	47.150s	23.731ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.621m	9.466ms	1	1	100.00
V2	stress_all	spi_device_stress_all	17.180s	1.774ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.610s	12.798us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.790s	14.511us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.590s	116.490us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.590s	116.490us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.830s	232.628us	1	1	100.00
		spi_device_csr_rw	2.560s	65.826us	1	1	100.00
		spi_device_csr_aliasing	5.970s	212.769us	1	1	100.00
		spi_device_same_csr_outstanding	4.050s	2.285ms	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.830s	232.628us	1	1	100.00
		spi_device_csr_rw	2.560s	65.826us	1	1	100.00
		spi_device_csr_aliasing	5.970s	212.769us	1	1	100.00
		spi_device_same_csr_outstanding	4.050s	2.285ms	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.870s	426.330us	1	1	100.00
		spi_device_tl_intg_err	13.710s	295.930us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	13.710s	295.930us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	2.187m	61.101ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.76604327386598525211312495521627907756240122939293174440377946203156672222969
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @    881675 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[89])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    881675 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @    881675 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[985])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.81235999795992422320372245076582747168183817082511983377982479217380561632153
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    971096 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    971096 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   1052096 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb18a4a [101100011000101001001010] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   1052096 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0xb18a4a [101100011000101001001010] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])