SPI_DEVICE/2P Simulation Results

Thursday April 24 2025 20:28:32 UTC

GitHub Revision: 0fa5019

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	5.545m	57.149ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.960s	22.928us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.620s	79.156us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	15.460s	357.849us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	6.360s	1.638ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.190s	265.349us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.620s	79.156us	1	1	100.00
		spi_device_csr_aliasing	6.360s	1.638ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.670s	12.982us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.210s	71.734us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.670s	345.163us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.710s	88.038us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	1.540s	1.860us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.700s	89.412us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.700s	89.412us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	10.070s	8.498ms	1	1	100.00
		spi_device_tpm_sts_read	1.640s	45.678us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	19.170s	27.410ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	21.440s	9.738ms	1	1	100.00
		spi_device_flash_all	22.180s	3.053ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	6.020s	396.527us	1	1	100.00
		spi_device_flash_all	22.180s	3.053ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	6.020s	396.527us	1	1	100.00
		spi_device_flash_all	22.180s	3.053ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	22.180s	3.053ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	6.650s	601.292us	1	1	100.00
		spi_device_flash_all	22.180s	3.053ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	6.650s	601.292us	1	1	100.00
		spi_device_flash_all	22.180s	3.053ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	6.650s	601.292us	1	1	100.00
		spi_device_flash_all	22.180s	3.053ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	6.650s	601.292us	1	1	100.00
		spi_device_flash_all	22.180s	3.053ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	6.650s	601.292us	1	1	100.00
		spi_device_flash_all	22.180s	3.053ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	12.890s	5.725ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	4.710s	342.926us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	4.710s	342.926us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	4.710s	342.926us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	21.840s	3.596ms	1	1	100.00
		spi_device_read_buffer_direct	3.280s	136.828us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	4.710s	342.926us	1	1	100.00
		spi_device_flash_all	22.180s	3.053ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	22.180s	3.053ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	22.180s	3.053ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	4.270s	140.695us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	4.270s	140.695us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	5.545m	57.149ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	53.430s	10.830ms	1	1	100.00
V2	stress_all	spi_device_stress_all	38.030s	18.633ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.690s	15.108us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.770s	47.987us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.540s	153.046us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.540s	153.046us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.960s	22.928us	1	1	100.00
		spi_device_csr_rw	2.620s	79.156us	1	1	100.00
		spi_device_csr_aliasing	6.360s	1.638ms	1	1	100.00
		spi_device_same_csr_outstanding	2.470s	53.472us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.960s	22.928us	1	1	100.00
		spi_device_csr_rw	2.620s	79.156us	1	1	100.00
		spi_device_csr_aliasing	6.360s	1.638ms	1	1	100.00
		spi_device_same_csr_outstanding	2.470s	53.472us	1	1	100.00
V2		TOTAL			21	22	95.45
V2S	tl_intg_err	spi_device_sec_cm	2.090s	73.986us	1	1	100.00
		spi_device_tl_intg_err	14.340s	290.621us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	14.340s	290.621us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.117m	17.953ms	1	1	100.00
		TOTAL			32	33	96.97

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:
  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.20222511976590712916465440165744283975571341901996893653530567698721662818983
      Line 71, in log /nightly/runs/scratch/master/spi_device_2p-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    865661 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    865661 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @    931661 ps: (spi_device_ram_cfg_vseq.sv:23) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === dst_ram_cfg (0x330c0b [1100110000110000001011] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @    931661 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)