SRAM_CTRL/MAIN Simulation Results

Thursday April 24 2025 20:28:32 UTC

GitHub Revision: 0fa5019

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	12.080s	527.363us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.710s	29.432us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.700s	46.504us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.440s	161.421us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.640s	23.524us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.400s	1.629ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.700s	46.504us	1	1	100.00
		sram_ctrl_csr_aliasing	1.640s	23.524us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	2.188m	86.182ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.045m	12.774ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	7.652m	7.584ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.671m	13.334ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	14.448m	92.019ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	6.284m	11.292ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	40.510s	11.518ms	1	1	100.00
V2	executable	sram_ctrl_executable	7.249m	89.813ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	14.030s	1.426ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.582m	22.058ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	53.950s	768.258us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	19.790s	2.095ms	1	1	100.00
		sram_ctrl_throughput_w_readback	12.480s	2.900ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	15.600s	5.977ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.980s	359.855us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	12.709m	37.179ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.640s	38.774us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.330s	35.418us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.330s	35.418us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.710s	29.432us	1	1	100.00
		sram_ctrl_csr_rw	1.700s	46.504us	1	1	100.00
		sram_ctrl_csr_aliasing	1.640s	23.524us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.500s	262.935us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.710s	29.432us	1	1	100.00
		sram_ctrl_csr_rw	1.700s	46.504us	1	1	100.00
		sram_ctrl_csr_aliasing	1.640s	23.524us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.500s	262.935us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	18.590s	15.429ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.770s	7.243us	0	1	0.00
		sram_ctrl_tl_intg_err	2.270s	851.751us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.770s	7.243us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.270s	851.751us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	15.600s	5.977ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	15.600s	5.977ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.700s	46.504us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	7.249m	89.813ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	7.249m	89.813ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	7.249m	89.813ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	40.510s	11.518ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	5.000s	701.058us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	18.590s	15.429ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	6.190s	727.596us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	12.080s	527.363us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	12.080s	527.363us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	7.249m	89.813ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.770s	7.243us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	40.510s	11.518ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.770s	7.243us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.770s	7.243us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	12.080s	527.363us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.770s	7.243us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	38.780s	2.536ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(depth_o <= *'(Depth))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.89478733083835563739007282576506507245790052892741749566604338288788864284587
      Line 98, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   7242904 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   7242904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---