SRAM_CTRL/RET Simulation Results

Thursday April 24 2025 20:28:32 UTC

GitHub Revision: 0fa5019

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	33.950s	604.772us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.920s	23.111us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.550s	39.233us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.550s	339.593us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.840s	16.522us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.520s	56.569us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.550s	39.233us	1	1	100.00
		sram_ctrl_csr_aliasing	1.840s	16.522us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.540s	140.362us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	4.530s	68.108us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	3.926m	7.953ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.615m	2.271ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	41.760s	3.511ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	7.209m	4.841ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	4.550s	877.512us	1	1	100.00
V2	executable	sram_ctrl_executable	9.101m	12.810ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	7.370s	934.075us	1	1	100.00
		sram_ctrl_partial_access_b2b	4.223m	52.161ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.890s	47.820us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	46.800s	296.342us	1	1	100.00
		sram_ctrl_throughput_w_readback	39.770s	263.082us	1	1	100.00
V2	regwen	sram_ctrl_regwen	1.549m	3.181ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.680s	50.245us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	22.468m	26.962ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.730s	65.191us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.050s	33.678us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.050s	33.678us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.920s	23.111us	1	1	100.00
		sram_ctrl_csr_rw	1.550s	39.233us	1	1	100.00
		sram_ctrl_csr_aliasing	1.840s	16.522us	1	1	100.00
		sram_ctrl_same_csr_outstanding	2.070s	41.496us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.920s	23.111us	1	1	100.00
		sram_ctrl_csr_rw	1.550s	39.233us	1	1	100.00
		sram_ctrl_csr_aliasing	1.840s	16.522us	1	1	100.00
		sram_ctrl_same_csr_outstanding	2.070s	41.496us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.930s	791.155us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.570s	3.371us	0	1	0.00
		sram_ctrl_tl_intg_err	3.330s	349.811us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.570s	3.371us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.330s	349.811us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	1.549m	3.181ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	1.549m	3.181ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.550s	39.233us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	9.101m	12.810ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	9.101m	12.810ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	9.101m	12.810ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	4.550s	877.512us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.350s	139.909us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.930s	791.155us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.180s	64.605us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	33.950s	604.772us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	33.950s	604.772us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	9.101m	12.810ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.570s	3.371us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	4.550s	877.512us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.570s	3.371us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.570s	3.371us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	33.950s	604.772us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.570s	3.371us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	12.930s	954.872us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.105667046128901693407626873601005793806324962439122248933779504326469069487644
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3371460 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3371460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---