UART Simulation Results

Thursday April 24 2025 20:28:32 UTC

GitHub Revision: 0fa5019

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	7.400s	6.237ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.520s	22.908us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.700s	17.154us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.640s	58.718us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.490s	119.671us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.960s	24.493us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.700s	17.154us	1	1	100.00
		uart_csr_aliasing	1.490s	119.671us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	19.110s	15.537ms	1	1	100.00
V2	parity	uart_smoke	7.400s	6.237ms	1	1	100.00
		uart_tx_rx	19.110s	15.537ms	1	1	100.00
V2	parity_error	uart_intr	41.100s	21.912ms	1	1	100.00
		uart_rx_parity_err	1.781m	86.192ms	1	1	100.00
V2	watermark	uart_tx_rx	19.110s	15.537ms	1	1	100.00
		uart_intr	41.100s	21.912ms	1	1	100.00
V2	fifo_full	uart_fifo_full	1.464m	72.819ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	46.330s	77.872ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	2.421m	149.349ms	1	1	100.00
V2	rx_frame_err	uart_intr	41.100s	21.912ms	1	1	100.00
V2	rx_break_err	uart_intr	41.100s	21.912ms	1	1	100.00
V2	rx_timeout	uart_intr	41.100s	21.912ms	1	1	100.00
V2	perf	uart_perf	16.816m	34.782ms	1	1	100.00
V2	sys_loopback	uart_loopback	3.350s	5.162ms	1	1	100.00
V2	line_loopback	uart_loopback	3.350s	5.162ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	14.080s	17.957ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	3.830s	4.381ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	3.640s	2.864ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	4.610s	3.065ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	3.689m	94.917ms	1	1	100.00
V2	stress_all	uart_stress_all	8.865m	33.795ms	1	1	100.00
V2	alert_test	uart_alert_test	1.570s	18.845us	1	1	100.00
V2	intr_test	uart_intr_test	1.410s	20.229us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.020s	208.560us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.020s	208.560us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.520s	22.908us	1	1	100.00
		uart_csr_rw	1.700s	17.154us	1	1	100.00
		uart_csr_aliasing	1.490s	119.671us	1	1	100.00
		uart_same_csr_outstanding	1.700s	20.406us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.520s	22.908us	1	1	100.00
		uart_csr_rw	1.700s	17.154us	1	1	100.00
		uart_csr_aliasing	1.490s	119.671us	1	1	100.00
		uart_same_csr_outstanding	1.700s	20.406us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.770s	128.178us	1	1	100.00
		uart_tl_intg_err	1.780s	79.003us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.780s	79.003us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	8.050s	1.543ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00