CHIP Simulation Results

Thursday April 24 2025 20:28:32 UTC

GitHub Revision: `0fa5019`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.623m	2.664ms	1	1	100.00
		chip_sw_example_rom	1.181m	2.439ms	1	1	100.00
		chip_sw_example_manufacturer	2.238m	3.373ms	1	1	100.00
		chip_sw_example_concurrency	2.790m	3.395ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.407m	5.082ms	1	1	100.00
V1	csr_rw	chip_csr_rw	2.693m	4.381ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	8.450m	7.839ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	55.229m	29.258ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	49.810s	2.612ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	55.229m	29.258ms	1	1	100.00
		chip_csr_rw	2.693m	4.381ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	6.540s	195.465us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.163m	4.166ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.163m	4.166ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.163m	4.166ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.167m	4.282ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.167m	4.282ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.838m	4.593ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.991m	4.179ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	6.157m	4.377ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	28.817m	13.728ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	5.801m	3.914ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	4.016m	4.799ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.071m	5.373ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.071m	5.373ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.173m	3.000ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.890m	3.036ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.519m	3.156ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	1.529m	2.333ms	1	1	100.00
		chip_tap_straps_testunlock0	5.921m	6.262ms	1	1	100.00
		chip_tap_straps_rma	2.690m	3.464ms	1	1	100.00
		chip_tap_straps_prod	1.501m	2.558ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	3.315m	2.641ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	12.738m	9.128ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	7.478m	5.395ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	7.478m	5.395ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	8.369m	6.874ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	41.029m	26.873ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.034m	3.779ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.419m	5.858ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	58.109m	19.532ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.360m	2.555ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	9.911m	6.933ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.887m	2.883ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	15.957m	9.232ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.728m	3.088ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.468m	5.130ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.400m	3.168ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.712m	2.704ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	7.567m	8.365ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.145m	5.708ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.365m	2.959ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.145m	5.708ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.439m	2.368ms	1	1	100.00
		chip_sw_aes_smoketest	1.990m	2.749ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.677m	2.524ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.256m	2.397ms	1	1	100.00
		chip_sw_csrng_smoketest	2.552m	2.742ms	1	1	100.00
		chip_sw_entropy_src_smoketest	4.874m	3.510ms	1	1	100.00
		chip_sw_gpio_smoketest	3.051m	3.559ms	1	1	100.00
		chip_sw_hmac_smoketest	3.175m	2.996ms	1	1	100.00
		chip_sw_kmac_smoketest	3.322m	3.583ms	1	1	100.00
		chip_sw_otbn_smoketest	11.256m	6.672ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.983m	5.975ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	5.270m	5.679ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.895m	3.436ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.535m	2.722ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.026m	2.813ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.791m	2.678ms	1	1	100.00
		chip_sw_uart_smoketest	2.228m	2.937ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.271m	2.589ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.833m	5.402ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.953h	60.218ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	40.978m	15.285ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.543m	5.096ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.124m	3.046ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.927m	3.017ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.821h	54.625ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.841h	55.035ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	53.800s	1.902ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	53.800s	1.902ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	55.229m	29.258ms	1	1	100.00
		chip_same_csr_outstanding	16.125m	15.346ms	1	1	100.00
		chip_csr_hw_reset	2.407m	5.082ms	1	1	100.00
		chip_csr_rw	2.693m	4.381ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	55.229m	29.258ms	1	1	100.00
		chip_same_csr_outstanding	16.125m	15.346ms	1	1	100.00
		chip_csr_hw_reset	2.407m	5.082ms	1	1	100.00
		chip_csr_rw	2.693m	4.381ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	19.720s	328.261us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.670s	44.758us	1	1	100.00
		xbar_smoke_large_delays	41.760s	6.109ms	1	1	100.00
		xbar_smoke_slow_rsp	47.410s	5.623ms	1	1	100.00
		xbar_random_zero_delays	21.060s	396.718us	1	1	100.00
		xbar_random_large_delays	4.513m	44.611ms	1	1	100.00
		xbar_random_slow_rsp	2.745m	17.458ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	30.880s	1.359ms	1	1	100.00
		xbar_error_and_unmapped_addr	11.930s	119.405us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	7.080s	66.787us	1	1	100.00
		xbar_error_and_unmapped_addr	11.930s	119.405us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	41.100s	1.148ms	1	1	100.00
		xbar_access_same_device_slow_rsp	11.929m	83.608ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	38.140s	2.476ms	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.932m	2.715ms	1	1	100.00
		xbar_stress_all_with_error	1.073m	2.472ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	4.420m	2.819ms	1	1	100.00
		xbar_stress_all_with_reset_error	4.832m	4.865ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	40.978m	15.285ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	33.861m	25.228ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	39.840m	15.130ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	31.229m	10.986ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	40.662m	15.655ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	40.697m	15.081ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	40.223m	16.116ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	38.721m	14.362ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	26.590s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	26.450s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	27.180s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	28.560s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	26.500s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	27.280s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	27.760s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	27.880s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	28.390s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	25.670s	10.260us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	25.700s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	27.310s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	24.790s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	27.710s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	25.270s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	25.370s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	25.910s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	25.360s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	25.090s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	27.900s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	25.140s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	25.620s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	27.810s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	25.310s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	24.620s	10.360us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	30.214m	11.119ms	1	1	100.00
		rom_e2e_asm_init_dev	37.133m	15.772ms	1	1	100.00
		rom_e2e_asm_init_prod	38.840m	15.564ms	1	1	100.00
		rom_e2e_asm_init_prod_end	36.916m	15.422ms	1	1	100.00
		rom_e2e_asm_init_rma	37.446m	14.944ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	36.286m	14.655ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	36.724m	14.907ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	37.159m	15.020ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	39.313m	15.449ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	6.070m	18.770ms	1	1	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	6.070m	18.770ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.609m	3.126ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.360m	2.555ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.237m	3.016ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.269m	3.259ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	9.987m	6.985ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.625m	2.554ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	6.456m	6.194ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	5.846m	5.675ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.488m	5.744ms	1	1	100.00
		chip_plic_all_irqs_10	4.349m	3.441ms	1	1	100.00
		chip_plic_all_irqs_20	5.512m	3.777ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	3.217m	3.777ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	14.160m	12.356ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	5.369m	4.894ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.097m	2.615ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	7.751m	9.147ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	20.289m	9.795ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	10.859m	5.437ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	12.618m	8.803ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.253h	254.846ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.851m	4.571ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.983m	5.975ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.851m	4.571ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.675m	8.314ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.675m	8.314ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	3.217m	6.165ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	5.014m	5.422ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	8.994m	5.770ms	1	1	100.00
		chip_sw_aes_idle	2.269m	3.259ms	1	1	100.00
		chip_sw_hmac_enc_idle	3.147m	3.167ms	1	1	100.00
		chip_sw_kmac_idle	2.852m	2.882ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	2.675m	3.533ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.815m	4.072ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.159m	3.686ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.900m	4.156ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	10.680m	11.558ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.767m	3.766ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.762m	4.603ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.974m	4.428ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.092m	4.742ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.592m	3.792ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.975m	4.817ms	1	1	100.00
		chip_sw_ast_clk_outputs	8.369m	6.874ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	10.127m	10.301ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.974m	4.428ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.092m	4.742ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.034m	3.779ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.419m	5.858ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	58.109m	19.532ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.360m	2.555ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	9.911m	6.933ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.887m	2.883ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	15.957m	9.232ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.728m	3.088ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.468m	5.130ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.400m	3.168ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.852m	2.654ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.412m	5.122ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.073m	7.166ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	49.879m	25.464ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.445m	2.962ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.440m	3.058ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	10.857m	9.073ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.929m	2.963ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.656m	4.822ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	18.710m	25.305ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	38.054m	23.060ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	8.369m	6.874ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.367m	5.027ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.932m	3.233ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	5.846m	5.675ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	20.289m	9.795ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	15.306m	7.491ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.165m	2.659ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	5.454m	7.233ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.294m	2.618ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	43.775m	17.041ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.478m	2.386ms	1	1	100.00
		chip_sw_edn_entropy_reqs	11.336m	5.713ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.478m	2.386ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	15.306m	7.491ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.756m	2.841ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	15.654m	22.580ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	8.080m	4.876ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.419m	5.858ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.758m	3.747ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.034m	3.779ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	57.886m	44.881ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	15.654m	22.580ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	2.794m	2.996ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	21.602m	11.223ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.203m	5.223ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	57.886m	44.881ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.203m	5.223ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.203m	5.223ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	5.203m	5.223ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.203m	5.223ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	5.846m	5.675ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	2.782m	8.421ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	7.905m	4.997ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.292m	5.252ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.292m	5.252ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.642m	2.167ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.887m	2.883ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	3.147m	3.167ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	3.133m	2.642ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	11.858m	6.455ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	5.711m	5.352ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	7.658m	5.582ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	6.467m	5.027ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.979m	4.528ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	21.602m	11.223ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	15.957m	9.232ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	22.532m	11.758ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	9.987m	6.985ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	45.351m	16.636ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	1.967m	3.125ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.769m	3.355ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.728m	3.088ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	21.602m	11.223ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	8.589m	10.479ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	3.463m	3.651ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	24.055m	11.435ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.852m	2.882ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	6.456m	6.194ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	1.529m	2.333ms	1	1	100.00
		chip_tap_straps_rma	2.690m	3.464ms	1	1	100.00
		chip_tap_straps_prod	1.501m	2.558ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	1.780m	2.679ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	8.589m	10.479ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	8.589m	10.479ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	8.589m	10.479ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	19.417m	9.471ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	5.203m	5.223ms	1	1	100.00
		chip_sw_flash_rma_unlocked	57.886m	44.881ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.177m	3.227ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.367m	6.474ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.458m	5.415ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	6.308m	5.938ms	1	1	100.00
		chip_sw_lc_ctrl_transition	8.589m	10.479ms	1	1	100.00
		chip_sw_keymgr_key_derivation	21.602m	11.223ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	4.719m	9.030ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	6.221m	6.253ms	1	1	100.00
		chip_prim_tl_access	2.782m	8.421ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	10.127m	10.301ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.767m	3.766ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.762m	4.603ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.974m	4.428ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.092m	4.742ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.592m	3.792ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.975m	4.817ms	1	1	100.00
		chip_tap_straps_dev	1.529m	2.333ms	1	1	100.00
		chip_tap_straps_rma	2.690m	3.464ms	1	1	100.00
		chip_tap_straps_prod	1.501m	2.558ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.164m	8.065ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.077m	3.433ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.646m	3.254ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.835m	4.038ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.428m	3.082ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	24.851m	27.974ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.164m	8.065ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	56.541m	47.244ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.046h	49.955ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	8.715m	10.643ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.004h	46.548ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	24.851m	27.974ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.291m	2.616ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.199m	2.445ms	1	1	100.00
		rom_volatile_raw_unlock	1.156m	2.822ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	55.967m	17.080ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	58.109m	19.532ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	8.994m	5.770ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	8.994m	5.770ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	8.994m	5.770ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	5.244m	3.378ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	8.589m	10.479ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	15.654m	22.580ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.244m	3.378ms	1	1	100.00
		chip_sw_keymgr_key_derivation	21.602m	11.223ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.666m	4.118ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.424m	2.503ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	15.654m	22.580ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.244m	3.378ms	1	1	100.00
		chip_sw_keymgr_key_derivation	21.602m	11.223ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.666m	4.118ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.424m	2.503ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	8.589m	10.479ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	5.459m	5.654ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	1.780m	2.679ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.177m	3.227ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.367m	6.474ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.458m	5.415ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	6.308m	5.938ms	1	1	100.00
		chip_sw_lc_ctrl_transition	8.589m	10.479ms	1	1	100.00
		chip_prim_tl_access	2.782m	8.421ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	2.782m	8.421ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	16.351m	8.490ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	4.376m	8.974ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	14.627m	26.032ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.349m	7.398ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	6.329m	9.351ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	4.521m	6.386ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	15.130m	25.948ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	11.016m	11.487ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	7.675m	8.314ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	9.183m	8.508ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.806m	5.094ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	4.376m	8.974ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.739m	3.994ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	28.583m	29.409ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.247m	6.723ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.511m	3.962ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	16.435m	20.942ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.703m	7.836ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	15.276m	12.682ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	22.544m	22.740ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.170m	2.384ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	5.846m	5.675ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	4.719m	9.030ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	4.719m	9.030ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	15.276m	12.682ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	16.435m	20.942ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	5.806m	5.094ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.983m	5.975ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	5.283m	4.674ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	4.996m	5.119ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.736m	3.888ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	14.160m	12.356ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.141m	2.762ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	5.846m	5.675ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	10.859m	5.437ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.003m	4.478ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	8.721m	5.161ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.218m	2.693ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.424m	2.503ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	4.996m	5.119ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	4.996m	5.119ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	10.848m	10.587ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	14.442m	14.031ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	5.283m	4.674ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	5.341m	4.944ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.112m	4.948ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	2.690m	3.464ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	3.164m	8.065ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.488m	5.744ms	1	1	100.00
		chip_plic_all_irqs_10	4.349m	3.441ms	1	1	100.00
		chip_plic_all_irqs_20	5.512m	3.777ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.123m	2.383ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.413m	2.950ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	40.978m	15.285ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	5.955m	6.208ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.711m	2.451ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	4.006m	3.833ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	3.017m	2.875ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	5.666m	4.118ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.468m	5.130ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	7.687m	8.300ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	5.318m	6.164ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	6.221m	6.253ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	5.846m	5.675ms	1	1	100.00
		chip_sw_data_integrity_escalation	7.478m	5.395ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.703m	7.836ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	20.368m	25.259ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.092m	2.833ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	2.787m	3.345ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.124m	4.948ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	20.368m	25.259ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	20.368m	25.259ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	13.341m	11.550ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	13.341m	11.550ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	5.052m	4.951ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	6.070m	18.770ms	1	1	100.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	1.811m	2.935ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	1.953m	2.899ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.843m	3.889ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.207m	4.649ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	16.473m	7.708ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.315h	31.467ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	26.808m	11.559ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.751m	2.974ms	1	1	100.00
V2		TOTAL			240	275	87.27
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.065m	3.020ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.308m	2.544ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.463h	71.248ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	6.069m	3.541ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	17.239m	11.901ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.798m	11.115ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.032m	11.601ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.750m	3.471ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.532m	3.824ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.331m	3.714ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	12.175s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.518m	4.602ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.399m	2.961ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	18.238m	7.052ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	20.375m	8.912ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.630m	2.783ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	7.675m	4.899ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.747m	3.162ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	4.675m	5.447ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.870m	5.135ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	3.871m	5.457ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	15.276m	12.682ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	17.239m	11.901ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.798m	11.115ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.032m	11.601ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	4.200m	5.296ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	5.846m	5.675ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.389h	38.258ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.389h	38.258ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.714m	3.708ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.167m	4.282ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	46.812m	18.622ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	2.527m	2.686ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.949m	4.964ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.510m	2.311ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.947m	2.461ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.531m	3.962ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.679s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.802m	3.528ms	1	1	100.00
		TOTAL			285	325	87.69

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.104782740101790210552209830077023438617264552222672303248385354791393040120245
    Line 696, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3392660597927531756989075171777893960916994519185503702517451084509038089246
    Line 736, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.82266737085950505212883661758421286199774120046932522364489114385227883706094
    Line 717, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.86749799753594164318549163806405120120476330121292505432475184722917387756677
    Line 714, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.66393176764831164698478434852431628027545603453919547384413500697519182395390
    Line 868, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.40126462965664613933503030621530310663882631320840491603003672643999865213688
    Line 727, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.88057215977724495256323616046494269860108865242738726580695901607365105373061
    Line 701, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.72092925284367409506126044882875080275375360512500167660806630852570304282074
    Line 758, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.46107909266787137818618242051279306640887154115406162823404937446017373989362
    Line 766, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.13538003529846269303910742384052690354932330025621918771370910591863013788923
    Line 687, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.71767470577805976995500618384946063313907103544169422265705336899965560588463
    Line 852, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.48222901107559397313207958104043906238762634349876526778564865441974010450950
    Line 710, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.59713709207783048120216879078828784255794834200848771342317016912712168504942
    Line 627, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.88374746169339796880468079737708504329992113494066905158045014680012665354024
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.152s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.49620432912691396692741114630078086348520052471642847887878954668252454520795
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 2.628s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.43871479039672176350544848426982372683822518030367722445389332761137787374382
    Line 953, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.35621565775743776442043654261115691671668285964088951044087663736537398570439
    Line 704, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.69024767865871656244308233442422490518209404757758464631496598931692896396946
    Line 1048, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.47531610068519173294207420132029828954700279420754852654837451065421906454433
    Line 639, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.7591381274049471642635721830558533933120579108664430132750845665509791542075
    Line 416, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2451.193432 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 2451.193432 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@120981) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.38221155399284598359860468418128027451822188110152063026477474076569896396408
Line 446, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 5119.058284 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@120981) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5119.058284 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:197)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.34768820576254454450800515493616996378645645803548586795785546596019081013280
    Line 414, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 11550.431448 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:197)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 11550.431448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.53748538190027107944967607073231616374265795114519015813105492172124528624984
    Line 411, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2554.066038 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 2554.066038 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.88469829929989608229221616090922361646325633370613022041241471054148444114067
    Line 407, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2614.896216 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2614.896216 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.19303652236483266595924310641607653828416772872350505864839032294829203084800
    Line 418, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2658.516502 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 2658.516502 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@39185) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.84754108199836788672974844677391918147043159045992791064392161069772618448708
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 1901.816464 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@39185) { a_addr: 'h10498  a_data: 'hb6d1039d  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1b  a_opcode: 'h4  a_user: 'h19554  d_param: 'h0  d_source: 'h1b  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1901.816464 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.11701727185599339683460929468759194750803869380507645516147431834439148743391
    Line 416, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2543.865208 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2543.865208 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.70768946269508604345341468775001717327485024317037059743688853306941193385739
    Line 411, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3045.550000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3045.550000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.104120874525937736387387110621925231348935837610865727206790385742583624336901
    Line 416, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3017.159000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3017.159000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.22664437184276829666264669563182874950984116170367813937529143424722007051670
    Line 429, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 26872.708494 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 26872.708494 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.84204235219793551247192689575384181205776096076544318235835972309803131050740
    Line 459, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3540.807451 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3540.807451 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.18108343414677067069729332746958461305410978103044332269447048091754304958283
    Line 762, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.87767036774041554571279991077973410513690066162635372446559477096729222254496
    Line 689, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32211) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.16265646251208214866749118630618398233262956399022927524613631873309978092143
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2611.874510 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32211) { a_addr: 'h10428  a_data: 'h1fd42c4a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h14  a_opcode: 'h4  a_user: 'h19980  d_param: 'h0  d_source: 'h14  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2611.874510 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---