ADC_CTRL Simulation Results

Monday April 28 2025 20:29:11 UTC

GitHub Revision: 841f73f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	11.800s	5.932ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.060s	872.484us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.200s	623.898us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	15.890s	52.308ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.640s	442.694us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	3.820s	549.967us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.200s	623.898us	1	1	100.00
		adc_ctrl_csr_aliasing	2.640s	442.694us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	13.312m	488.858ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	5.244m	166.219ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	1.266m	160.761ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	9.284m	322.724ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	2.950m	371.670ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	5.478m	410.106ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	8.901m	323.596ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	39.470s	159.098ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	2.100s	4.499ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	12.010s	22.872ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	1.109m	137.456ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	5.657m	282.485ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.810s	392.876us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	2.430s	434.903us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.630s	852.598us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.630s	852.598us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.060s	872.484us	1	1	100.00
		adc_ctrl_csr_rw	2.200s	623.898us	1	1	100.00
		adc_ctrl_csr_aliasing	2.640s	442.694us	1	1	100.00
		adc_ctrl_same_csr_outstanding	8.760s	4.380ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.060s	872.484us	1	1	100.00
		adc_ctrl_csr_rw	2.200s	623.898us	1	1	100.00
		adc_ctrl_csr_aliasing	2.640s	442.694us	1	1	100.00
		adc_ctrl_same_csr_outstanding	8.760s	4.380ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	11.690s	4.498ms	1	1	100.00
		adc_ctrl_tl_intg_err	7.370s	4.702ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	7.370s	4.702ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	11.390s	14.440ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00