EDN Simulation Results

Monday April 28 2025 20:29:11 UTC

GitHub Revision: 841f73f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.820s	102.440us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.700s	47.763us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.780s	14.772us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.200s	306.756us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.980s	34.881us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.820s	95.827us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.780s	14.772us	1	1	100.00
		edn_csr_aliasing	1.980s	34.881us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.890s	125.147us	1	1	100.00
V2	csrng_commands	edn_genbits	1.890s	125.147us	1	1	100.00
V2	genbits	edn_genbits	1.890s	125.147us	1	1	100.00
V2	interrupts	edn_intr	2.000s	28.712us	1	1	100.00
V2	alerts	edn_alert	1.950s	41.295us	1	1	100.00
V2	errs	edn_err	2.010s	23.421us	1	1	100.00
V2	disable	edn_disable	1.730s	21.026us	1	1	100.00
		edn_disable_auto_req_mode	1.820s	67.150us	1	1	100.00
V2	stress_all	edn_stress_all	4.520s	331.923us	1	1	100.00
V2	intr_test	edn_intr_test	1.700s	53.589us	1	1	100.00
V2	alert_test	edn_alert_test	1.800s	34.918us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.820s	263.801us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.820s	263.801us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.700s	47.763us	1	1	100.00
		edn_csr_rw	1.780s	14.772us	1	1	100.00
		edn_csr_aliasing	1.980s	34.881us	1	1	100.00
		edn_same_csr_outstanding	1.660s	24.446us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.700s	47.763us	1	1	100.00
		edn_csr_rw	1.780s	14.772us	1	1	100.00
		edn_csr_aliasing	1.980s	34.881us	1	1	100.00
		edn_same_csr_outstanding	1.660s	24.446us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	7.630s	2.738ms	1	1	100.00
		edn_tl_intg_err	3.110s	237.676us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.640s	16.402us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.950s	41.295us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	7.630s	2.738ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	7.630s	2.738ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	7.630s	2.738ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	7.630s	2.738ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.950s	41.295us	1	1	100.00
		edn_sec_cm	7.630s	2.738ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.950s	41.295us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.110s	237.676us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	58.370s	3.743ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00