HMAC Simulation Results

Monday April 28 2025 20:29:11 UTC

GitHub Revision: 841f73f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 9.490s 991.147us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.500s 75.579us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.630s 110.409us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 10.050s 552.887us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 4.890s 765.949us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.740s 18.938us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.630s 110.409us 1 1 100.00
hmac_csr_aliasing 4.890s 765.949us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 39.580s 1.050ms 1 1 100.00
V2 back_pressure hmac_back_pressure 9.730s 3.979ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.320s 183.893us 1 1 100.00
hmac_test_sha384_vectors 7.511m 14.545ms 1 1 100.00
hmac_test_sha512_vectors 6.487m 54.080ms 1 1 100.00
hmac_test_hmac256_vectors 8.360s 521.981us 1 1 100.00
hmac_test_hmac384_vectors 7.990s 287.360us 1 1 100.00
hmac_test_hmac512_vectors 10.180s 1.198ms 1 1 100.00
V2 burst_wr hmac_burst_wr 16.570s 5.619ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 19.210s 301.629us 1 1 100.00
V2 error hmac_error 8.730s 6.507ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.373m 2.422ms 1 1 100.00
V2 save_and_restore hmac_smoke 9.490s 991.147us 1 1 100.00
hmac_long_msg 39.580s 1.050ms 1 1 100.00
hmac_back_pressure 9.730s 3.979ms 1 1 100.00
hmac_datapath_stress 19.210s 301.629us 1 1 100.00
hmac_burst_wr 16.570s 5.619ms 1 1 100.00
hmac_stress_all 4.960m 17.571ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 9.490s 991.147us 1 1 100.00
hmac_long_msg 39.580s 1.050ms 1 1 100.00
hmac_back_pressure 9.730s 3.979ms 1 1 100.00
hmac_datapath_stress 19.210s 301.629us 1 1 100.00
hmac_wipe_secret 1.373m 2.422ms 1 1 100.00
hmac_test_sha256_vectors 8.320s 183.893us 1 1 100.00
hmac_test_sha384_vectors 7.511m 14.545ms 1 1 100.00
hmac_test_sha512_vectors 6.487m 54.080ms 1 1 100.00
hmac_test_hmac256_vectors 8.360s 521.981us 1 1 100.00
hmac_test_hmac384_vectors 7.990s 287.360us 1 1 100.00
hmac_test_hmac512_vectors 10.180s 1.198ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 9.490s 991.147us 1 1 100.00
hmac_long_msg 39.580s 1.050ms 1 1 100.00
hmac_back_pressure 9.730s 3.979ms 1 1 100.00
hmac_datapath_stress 19.210s 301.629us 1 1 100.00
hmac_burst_wr 16.570s 5.619ms 1 1 100.00
hmac_error 8.730s 6.507ms 1 1 100.00
hmac_wipe_secret 1.373m 2.422ms 1 1 100.00
hmac_test_sha256_vectors 8.320s 183.893us 1 1 100.00
hmac_test_sha384_vectors 7.511m 14.545ms 1 1 100.00
hmac_test_sha512_vectors 6.487m 54.080ms 1 1 100.00
hmac_test_hmac256_vectors 8.360s 521.981us 1 1 100.00
hmac_test_hmac384_vectors 7.990s 287.360us 1 1 100.00
hmac_test_hmac512_vectors 10.180s 1.198ms 1 1 100.00
hmac_stress_all 4.960m 17.571ms 1 1 100.00
V2 stress_all hmac_stress_all 4.960m 17.571ms 1 1 100.00
V2 alert_test hmac_alert_test 1.510s 28.242us 1 1 100.00
V2 intr_test hmac_intr_test 1.370s 29.470us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.670s 77.019us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.670s 77.019us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.500s 75.579us 1 1 100.00
hmac_csr_rw 1.630s 110.409us 1 1 100.00
hmac_csr_aliasing 4.890s 765.949us 1 1 100.00
hmac_same_csr_outstanding 2.580s 311.287us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.500s 75.579us 1 1 100.00
hmac_csr_rw 1.630s 110.409us 1 1 100.00
hmac_csr_aliasing 4.890s 765.949us 1 1 100.00
hmac_same_csr_outstanding 2.580s 311.287us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.760s 159.520us 1 1 100.00
hmac_tl_intg_err 2.800s 101.307us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.800s 101.307us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 9.490s 991.147us 1 1 100.00
V3 stress_reset hmac_stress_reset 4.270s 169.885us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 2.230m 10.853ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.650s 111.407us 1 1 100.00
TOTAL 28 28 100.00