I2C Simulation Results

Monday April 28 2025 20:29:11 UTC

GitHub Revision: 841f73f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	18.420s	1.783ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	21.430s	953.924us	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.750s	28.838us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.700s	21.579us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.030s	184.537us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.990s	45.446us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.960s	30.611us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.700s	21.579us	1	1	100.00
		i2c_csr_aliasing	1.990s	45.446us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.790s	116.896us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	3.787m	47.828ms	1	1	100.00
V2	host_maxperf	i2c_host_perf	4.380s	424.007us	1	1	100.00
V2	host_override	i2c_host_override	1.590s	39.066us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	2.522m	7.964ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.080m	3.425ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.110s	491.037us	1	1	100.00
		i2c_host_fifo_fmt_empty	15.860s	415.646us	1	1	100.00
		i2c_host_fifo_reset_rx	10.880s	803.881us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.522m	14.121ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	9.640s	1.166ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.730s	220.762us	0	1	0.00
V2	target_glitch	i2c_target_glitch	8.710s	15.240ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	1.216m	20.758ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	5.120s	660.343us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	16.040s	6.734ms	1	1	100.00
		i2c_target_intr_smoke	6.510s	24.247ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.600s	308.835us	1	1	100.00
		i2c_target_fifo_reset_tx	1.950s	774.018us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	33.230s	20.784ms	1	1	100.00
		i2c_target_stress_rd	16.040s	6.734ms	1	1	100.00
		i2c_target_intr_stress_wr	42.440s	12.057ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	6.780s	2.740ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	5.900s	3.183ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.170s	2.547ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	3.930s	933.635us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.750s	366.420us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.910s	104.441us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	4.380s	424.007us	1	1	100.00
		i2c_host_perf_precise	2.350s	446.633us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	9.640s	1.166ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	6.010s	496.361us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.020s	517.318us	1	1	100.00
		i2c_target_nack_acqfull_addr	3.060s	393.415us	1	1	100.00
		i2c_target_nack_txstretch	1.930s	1.231ms	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	5.740s	466.048us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	3.460s	3.665ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.600s	37.790us	1	1	100.00
V2	intr_test	i2c_intr_test	1.660s	18.461us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	3.010s	125.192us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	3.010s	125.192us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.750s	28.838us	1	1	100.00
		i2c_csr_rw	1.700s	21.579us	1	1	100.00
		i2c_csr_aliasing	1.990s	45.446us	1	1	100.00
		i2c_same_csr_outstanding	2.220s	109.032us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.750s	28.838us	1	1	100.00
		i2c_csr_rw	1.700s	21.579us	1	1	100.00
		i2c_csr_aliasing	1.990s	45.446us	1	1	100.00
		i2c_same_csr_outstanding	2.220s	109.032us	1	1	100.00
V2		TOTAL			37	38	97.37
V2S	tl_intg_err	i2c_tl_intg_err	2.550s	896.491us	1	1	100.00
		i2c_sec_cm	1.820s	229.441us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.550s	896.491us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	5.670s	827.037us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.550s	666.753us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	7.760s	479.142us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			46	50	92.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.71588346626280235328748127599858519203079315321126022152943323719033862121320
      Line 105, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 827037061 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 827037061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.38018711005660200765376490959093514291847454782639340381134633523232932362978
      Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 479142372 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 479142372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.24794516935363411608449415133249695685955338543970997360942585064483344878098
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 666753441 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 223 [0xdf])
        UVM_INFO @ 666753441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.112525166290721080592432387215333494773753348246623147352620235033179959015716
      Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_FATAL @ 220761997 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x465d5194, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
        UVM_INFO @ 220761997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---