KEYMGR Simulation Results

Monday April 28 2025 20:29:11 UTC

GitHub Revision: 841f73f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	3.170s	53.271us	1	1	100.00
V1	random	keymgr_random	8.950s	560.814us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.740s	59.060us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.740s	33.254us	0	1	0.00
V1	csr_bit_bash	keymgr_csr_bit_bash	5.000s	1.853ms	0	1	0.00
V1	csr_aliasing	keymgr_csr_aliasing	3.350s	158.776us	0	1	0.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.810s	191.374us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.740s	33.254us	0	1	0.00
		keymgr_csr_aliasing	3.350s	158.776us	0	1	0.00
V1		TOTAL			4	7	57.14
V2	cfgen_during_op	keymgr_cfg_regwen	4.610s	144.462us	1	1	100.00
V2	sideload	keymgr_sideload	4.110s	98.271us	1	1	100.00
		keymgr_sideload_kmac	3.440s	196.732us	1	1	100.00
		keymgr_sideload_aes	3.050s	199.724us	1	1	100.00
		keymgr_sideload_otbn	4.000s	320.979us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.800s	26.581us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	4.070s	137.017us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.050s	152.456us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	6.620s	231.430us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	2.940s	49.579us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	6.440s	402.653us	1	1	100.00
V2	stress_all	keymgr_stress_all	28.580s	3.949ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.700s	34.234us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.610s	12.206us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.190s	57.277us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.190s	57.277us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.740s	59.060us	1	1	100.00
		keymgr_csr_rw	1.740s	33.254us	0	1	0.00
		keymgr_csr_aliasing	3.350s	158.776us	0	1	0.00
		keymgr_same_csr_outstanding	2.960s	67.740us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.740s	59.060us	1	1	100.00
		keymgr_csr_rw	1.740s	33.254us	0	1	0.00
		keymgr_csr_aliasing	3.350s	158.776us	0	1	0.00
		keymgr_same_csr_outstanding	2.960s	67.740us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	8.520s	1.916ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	8.520s	1.916ms	1	1	100.00
		keymgr_tl_intg_err	4.910s	194.506us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	3.620s	219.246us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	3.620s	219.246us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	3.620s	219.246us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	3.620s	219.246us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	6.260s	650.800us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	8.520s	1.916ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	8.520s	1.916ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	4.910s	194.506us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	3.620s	219.246us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	4.610s	144.462us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	8.950s	560.814us	1	1	100.00
		keymgr_csr_rw	1.740s	33.254us	0	1	0.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	8.950s	560.814us	1	1	100.00
		keymgr_csr_rw	1.740s	33.254us	0	1	0.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	8.950s	560.814us	1	1	100.00
		keymgr_csr_rw	1.740s	33.254us	0	1	0.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	4.070s	137.017us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	2.940s	49.579us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	2.940s	49.579us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	8.950s	560.814us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	3.190s	56.114us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	8.520s	1.916ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	8.520s	1.916ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	8.520s	1.916ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	3.420s	81.998us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	4.070s	137.017us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	8.520s	1.916ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	8.520s	1.916ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	8.520s	1.916ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	3.420s	81.998us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	3.420s	81.998us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	8.520s	1.916ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	3.420s	81.998us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	8.520s	1.916ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	3.420s	81.998us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	12.100s	416.055us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	30	90.00

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 3 failures:

  • Test keymgr_csr_rw has 1 failures.

    • 0.keymgr_csr_rw.66020778528862160894424991309889215517532399900878709829019570148225091217034
      Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[8] & 'hffffffff)))'
        UVM_ERROR @  33253737 ps: (keymgr_csr_assert_fpv.sv:406) [ASSERT FAILED] sealing_sw_binding_3_rd_A
        UVM_INFO @  33253737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_bit_bash has 1 failures.

    • 0.keymgr_csr_bit_bash.60256634920990826094019940877501030754498902836900779161557240562637679637849
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[17] & 'hffffffff)))'
        UVM_ERROR @ 1852721052 ps: (keymgr_csr_assert_fpv.sv:451) [ASSERT FAILED] attest_sw_binding_4_rd_A
        UVM_INFO @ 1852721052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_aliasing has 1 failures.

    • 0.keymgr_csr_aliasing.44711520071130418954340932932519591775505979600984854363438847156111005337775
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_aliasing/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[7] & 'hffffffff)))'
        UVM_ERROR @ 158776201 ps: (keymgr_csr_assert_fpv.sv:401) [ASSERT FAILED] sealing_sw_binding_2_rd_A
        UVM_INFO @ 158776201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---