KMAC/MASKED Simulation Results

Monday April 28 2025 20:29:11 UTC

GitHub Revision: 841f73f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.026m	21.396ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.890s	64.045us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.840s	22.379us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	8.980s	722.964us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.480s	1.505ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.190s	217.272us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.840s	22.379us	1	1	100.00
		kmac_csr_aliasing	4.480s	1.505ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.660s	16.453us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.110s	131.354us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	26.861m	73.646ms	1	1	100.00
V2	burst_write	kmac_burst_write	2.597m	12.961ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	30.810s	11.262ms	1	1	100.00
		kmac_test_vectors_sha3_256	21.595m	16.777ms	1	1	100.00
		kmac_test_vectors_sha3_384	18.500m	88.177ms	1	1	100.00
		kmac_test_vectors_sha3_512	15.790s	1.240ms	1	1	100.00
		kmac_test_vectors_shake_128	1.885m	3.936ms	1	1	100.00
		kmac_test_vectors_shake_256	22.416m	35.558ms	1	1	100.00
		kmac_test_vectors_kmac	3.190s	156.769us	1	1	100.00
		kmac_test_vectors_kmac_xof	4.160s	480.714us	1	1	100.00
V2	sideload	kmac_sideload	42.330s	11.723ms	1	1	100.00
V2	app	kmac_app	1.990m	3.331ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	19.330s	4.133ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.691m	11.689ms	1	1	100.00
V2	error	kmac_error	5.587m	70.299ms	1	1	100.00
V2	key_error	kmac_key_error	3.980s	588.773us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.580s	286.258us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	16.500s	4.423ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	2.010s	32.968us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	45.490s	6.326ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.330s	78.727us	1	1	100.00
V2	stress_all	kmac_stress_all	3.019m	26.398ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.630s	45.564us	1	1	100.00
V2	alert_test	kmac_alert_test	1.790s	54.993us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.250s	536.190us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.250s	536.190us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.890s	64.045us	1	1	100.00
		kmac_csr_rw	1.840s	22.379us	1	1	100.00
		kmac_csr_aliasing	4.480s	1.505ms	1	1	100.00
		kmac_same_csr_outstanding	2.230s	64.775us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.890s	64.045us	1	1	100.00
		kmac_csr_rw	1.840s	22.379us	1	1	100.00
		kmac_csr_aliasing	4.480s	1.505ms	1	1	100.00
		kmac_same_csr_outstanding	2.230s	64.775us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.820s	506.220us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.820s	506.220us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.820s	506.220us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.820s	506.220us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.660s	18.281us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	27.330s	8.549ms	1	1	100.00
		kmac_tl_intg_err	4.670s	1.543ms	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.670s	1.543ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.330s	78.727us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.026m	21.396ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	42.330s	11.723ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.820s	506.220us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	27.330s	8.549ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	27.330s	8.549ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	27.330s	8.549ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.026m	21.396ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.330s	78.727us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	27.330s	8.549ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	27.150s	1.355ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.026m	21.396ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.237m	4.385ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.93417908870615243375969764295836173705789519271899398151998618811091660960524
      Line 116, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4384986984 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 4384986984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.47998817246395623078515057178830272157959421496878215776747388271857350581279
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[39] & 'hffffffff)))'
        UVM_ERROR @  18280976 ps: (kmac_csr_assert_fpv.sv:492) [ASSERT FAILED] prefix_0_rd_A
        UVM_INFO @  18280976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---