PATTGEN Simulation Results

Monday April 28 2025 20:29:11 UTC

GitHub Revision: `841f73f`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	16.000s	122.252us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	4.000s	15.870us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	4.000s	35.106us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	362.564us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	4.000s	122.890us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	76.925us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	4.000s	35.106us	1	1	100.00
		pattgen_csr_aliasing	4.000s	122.890us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	20.333m	600.000ms	0	1	0.00
V2	cnt_rollover	cnt_rollover	28.000s	2.719ms	1	1	100.00
V2	error	pattgen_error	13.000s	42.819us	1	1	100.00
V2	stress_all	pattgen_stress_all	5.000s	254.998us	1	1	100.00
V2	alert_test	pattgen_alert_test	4.000s	35.020us	1	1	100.00
V2	intr_test	pattgen_intr_test	3.000s	67.318us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	289.804us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	289.804us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	4.000s	15.870us	1	1	100.00
		pattgen_csr_rw	4.000s	35.106us	1	1	100.00
		pattgen_csr_aliasing	4.000s	122.890us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	30.968us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	4.000s	15.870us	1	1	100.00
		pattgen_csr_rw	4.000s	35.106us	1	1	100.00
		pattgen_csr_aliasing	4.000s	122.890us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	30.968us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	379.435us	1	1	100.00
		pattgen_sec_cm	9.000s	62.155us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	379.435us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	40.000s	19.112ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	2.100m	10.004ms	0	1	0.00
		TOTAL			15	18	83.33

Failure Buckets

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test pattgen_perf has 1 failures.
  - 0.pattgen_perf.70293915426564120053775608210308348663182385316237364781417316734956037849192
    Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 0.pattgen_inactive_level.96376329216891343646286829327260728815629235269248126863012754549722156235790
    Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10003974936 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x94178d50, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
  UVM_INFO @ 10003974936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_vseq.sv:929) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test pattgen_stress_all_with_rand_reset has 1 failures.

0.pattgen_stress_all_with_rand_reset.21797394829023844979242652356267543239416771055792077191320542910413781112128
Line 110, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 749413687 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 749451758 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 749451758 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/5
  UVM_INFO @ 750023190 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]