ROM_CTRL/32KB Simulation Results

Monday April 28 2025 20:29:11 UTC

GitHub Revision: 841f73f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 5.700s 523.219us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 6.240s 391.300us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 5.230s 957.908us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 4.540s 605.081us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.400s 126.149us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 5.200s 1.481ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 5.230s 957.908us 1 1 100.00
rom_ctrl_csr_aliasing 4.400s 126.149us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 5.680s 2.094ms 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 5.320s 466.674us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 5.650s 2.260ms 1 1 100.00
V2 stress_all rom_ctrl_stress_all 16.030s 434.000us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 6.990s 1.713ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.490s 2.107ms 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 7.780s 336.759us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 7.780s 336.759us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 6.240s 391.300us 1 1 100.00
rom_ctrl_csr_rw 5.230s 957.908us 1 1 100.00
rom_ctrl_csr_aliasing 4.400s 126.149us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.310s 570.875us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 6.240s 391.300us 1 1 100.00
rom_ctrl_csr_rw 5.230s 957.908us 1 1 100.00
rom_ctrl_csr_aliasing 4.400s 126.149us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.310s 570.875us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 14.520s 801.334us 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 3.233m 1.109ms 1 1 100.00
rom_ctrl_tl_intg_err 21.930s 828.304us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 3.233m 1.109ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 3.233m 1.109ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 3.233m 1.109ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 3.233m 1.109ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 5.700s 523.219us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 5.700s 523.219us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 5.700s 523.219us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 21.930s 828.304us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_kmac_err_chk 6.990s 1.713ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 14.520s 801.334us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 3.233m 1.109ms 1 1 100.00
V2S TOTAL 3 4 75.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 3.100m 8.441ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 18 19 94.74

Failure Buckets