ROM_CTRL/64KB Simulation Results

Monday April 28 2025 20:29:11 UTC

GitHub Revision: 841f73f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 10.470s 547.313us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 10.210s 303.845us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 7.240s 297.508us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 8.330s 293.747us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 7.530s 384.024us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 10.230s 4.061ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.240s 297.508us 1 1 100.00
rom_ctrl_csr_aliasing 7.530s 384.024us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.690s 545.036us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 5.900s 385.044us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 8.530s 307.851us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 19.920s 3.373ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 15.560s 3.583ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 7.960s 286.419us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 9.980s 289.757us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 9.980s 289.757us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 10.210s 303.845us 1 1 100.00
rom_ctrl_csr_rw 7.240s 297.508us 1 1 100.00
rom_ctrl_csr_aliasing 7.530s 384.024us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.100s 726.489us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 10.210s 303.845us 1 1 100.00
rom_ctrl_csr_rw 7.240s 297.508us 1 1 100.00
rom_ctrl_csr_aliasing 7.530s 384.024us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.100s 726.489us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 25.650s 5.670ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 5.030m 4.313ms 1 1 100.00
rom_ctrl_tl_intg_err 1.085m 8.252ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 5.030m 4.313ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 5.030m 4.313ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 5.030m 4.313ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 5.030m 4.313ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 10.470s 547.313us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 10.470s 547.313us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 10.470s 547.313us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.085m 8.252ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_kmac_err_chk 15.560s 3.583ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 25.650s 5.670ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 5.030m 4.313ms 1 1 100.00
V2S TOTAL 3 4 75.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 31.460s 2.224ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 18 19 94.74

Failure Buckets