RV_TIMER Simulation Results

Monday April 28 2025 20:29:11 UTC

GitHub Revision: 841f73f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.570s	33.602us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.440s	15.543us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.590s	56.840us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.740s	126.586us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.490s	31.502us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.670s	264.846us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.590s	56.840us	1	1	100.00
		rv_timer_csr_aliasing	1.490s	31.502us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.730s	367.749us	1	1	100.00
V2	disabled	rv_timer_disabled	1.073m	112.713ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	5.756m	315.843ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	5.756m	315.843ms	1	1	100.00
V2	stress	rv_timer_stress_all	2.380m	158.998ms	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.470s	16.334us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.270s	337.317us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.270s	337.317us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.440s	15.543us	1	1	100.00
		rv_timer_csr_rw	1.590s	56.840us	1	1	100.00
		rv_timer_csr_aliasing	1.490s	31.502us	1	1	100.00
		rv_timer_same_csr_outstanding	1.620s	110.155us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.440s	15.543us	1	1	100.00
		rv_timer_csr_rw	1.590s	56.840us	1	1	100.00
		rv_timer_csr_aliasing	1.490s	31.502us	1	1	100.00
		rv_timer_same_csr_outstanding	1.620s	110.155us	1	1	100.00
V2		TOTAL			7	7	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.680s	84.441us	1	1	100.00
		rv_timer_tl_intg_err	2.070s	112.932us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.070s	112.932us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	54.520s	6.984ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			16	16	100.00