SPI_DEVICE/1R1W Simulation Results

Monday April 28 2025 20:29:11 UTC

GitHub Revision: 841f73f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.565m	77.985ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.150s	101.598us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.970s	70.682us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	10.060s	1.250ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	7.130s	314.184us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.680s	38.353us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.970s	70.682us	1	1	100.00
		spi_device_csr_aliasing	7.130s	314.184us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	2.030s	12.769us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.070s	18.929us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	2.060s	22.616us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.550s	1.807us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.960s	1.894us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.990s	144.476us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.990s	144.476us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	4.020s	1.769ms	1	1	100.00
		spi_device_tpm_sts_read	1.940s	398.101us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	16.710s	4.882ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	10.030s	16.408ms	1	1	100.00
		spi_device_flash_all	1.700s	425.892us	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	5.050s	444.504us	1	1	100.00
		spi_device_flash_all	1.700s	425.892us	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	5.050s	444.504us	1	1	100.00
		spi_device_flash_all	1.700s	425.892us	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.700s	425.892us	1	1	100.00
V2	cmd_read_status	spi_device_intercept	22.760s	3.662ms	1	1	100.00
		spi_device_flash_all	1.700s	425.892us	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	22.760s	3.662ms	1	1	100.00
		spi_device_flash_all	1.700s	425.892us	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	22.760s	3.662ms	1	1	100.00
		spi_device_flash_all	1.700s	425.892us	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	22.760s	3.662ms	1	1	100.00
		spi_device_flash_all	1.700s	425.892us	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	22.760s	3.662ms	1	1	100.00
		spi_device_flash_all	1.700s	425.892us	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	24.030s	39.658ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	4.520s	215.342us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	4.520s	215.342us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	4.520s	215.342us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	24.760s	2.642ms	1	1	100.00
		spi_device_read_buffer_direct	10.730s	1.442ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	4.520s	215.342us	1	1	100.00
		spi_device_flash_all	1.700s	425.892us	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.700s	425.892us	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.700s	425.892us	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.760s	437.519us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.760s	437.519us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.565m	77.985ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	29.740s	2.064ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.900s	40.761us	1	1	100.00
V2	alert_test	spi_device_alert_test	1.740s	141.325us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.500s	11.717us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.860s	39.381us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.860s	39.381us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.150s	101.598us	1	1	100.00
		spi_device_csr_rw	2.970s	70.682us	1	1	100.00
		spi_device_csr_aliasing	7.130s	314.184us	1	1	100.00
		spi_device_same_csr_outstanding	2.380s	485.018us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.150s	101.598us	1	1	100.00
		spi_device_csr_rw	2.970s	70.682us	1	1	100.00
		spi_device_csr_aliasing	7.130s	314.184us	1	1	100.00
		spi_device_same_csr_outstanding	2.380s	485.018us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.960s	73.101us	1	1	100.00
		spi_device_tl_intg_err	6.040s	402.762us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	6.040s	402.762us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	25.530s	2.769ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.99012132292021674084499274468177334403308409457188510444897698890359731945334
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1270481 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[84])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1270481 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1270481 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[980])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.98492488286839486780918190747439447770618085791971621775066366563753929852623
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1180661 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1180661 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   1268661 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x130954 [100110000100101010100] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   1268661 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0x130954 [100110000100101010100] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])