SPI_DEVICE/2P Simulation Results

Monday April 28 2025 20:29:11 UTC

GitHub Revision: 841f73f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	56.820s	11.437ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.770s	41.676us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	3.030s	183.921us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	29.190s	22.529ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	6.500s	1.349ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.260s	546.588us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.030s	183.921us	1	1	100.00
		spi_device_csr_aliasing	6.500s	1.349ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.750s	30.587us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.700s	191.923us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.710s	19.067us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.960s	17.961us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	1.600s	2.570us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	3.670s	199.285us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	3.670s	199.285us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	1.920s	414.534us	1	1	100.00
		spi_device_tpm_sts_read	1.670s	27.835us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	26.540s	18.492ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	4.190s	606.480us	1	1	100.00
		spi_device_flash_all	1.750s	10.448us	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	4.320s	3.169ms	1	1	100.00
		spi_device_flash_all	1.750s	10.448us	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	4.320s	3.169ms	1	1	100.00
		spi_device_flash_all	1.750s	10.448us	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.750s	10.448us	1	1	100.00
V2	cmd_read_status	spi_device_intercept	10.530s	1.309ms	1	1	100.00
		spi_device_flash_all	1.750s	10.448us	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	10.530s	1.309ms	1	1	100.00
		spi_device_flash_all	1.750s	10.448us	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	10.530s	1.309ms	1	1	100.00
		spi_device_flash_all	1.750s	10.448us	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	10.530s	1.309ms	1	1	100.00
		spi_device_flash_all	1.750s	10.448us	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	10.530s	1.309ms	1	1	100.00
		spi_device_flash_all	1.750s	10.448us	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	22.170s	82.164ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	19.300s	5.752ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	19.300s	5.752ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	19.300s	5.752ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	5.770s	139.909us	1	1	100.00
		spi_device_read_buffer_direct	4.140s	233.250us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	19.300s	5.752ms	1	1	100.00
		spi_device_flash_all	1.750s	10.448us	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.750s	10.448us	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.750s	10.448us	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.860s	41.283us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.860s	41.283us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	56.820s	11.437ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	25.980s	16.245ms	1	1	100.00
V2	stress_all	spi_device_stress_all	8.808m	363.416ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.800s	14.678us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.580s	158.218us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.870s	284.296us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.870s	284.296us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.770s	41.676us	1	1	100.00
		spi_device_csr_rw	3.030s	183.921us	1	1	100.00
		spi_device_csr_aliasing	6.500s	1.349ms	1	1	100.00
		spi_device_same_csr_outstanding	3.710s	103.671us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.770s	41.676us	1	1	100.00
		spi_device_csr_rw	3.030s	183.921us	1	1	100.00
		spi_device_csr_aliasing	6.500s	1.349ms	1	1	100.00
		spi_device_same_csr_outstanding	3.710s	103.671us	1	1	100.00
V2		TOTAL			21	22	95.45
V2S	tl_intg_err	spi_device_sec_cm	2.240s	96.506us	1	1	100.00
		spi_device_tl_intg_err	12.660s	737.984us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	12.660s	737.984us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	4.687m	77.269ms	1	1	100.00
		TOTAL			32	33	96.97

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:
  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.100205310046913167545503932770879324748196693985557053875424553697439238166244
      Line 71, in log /nightly/runs/scratch/master/spi_device_2p-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1731622 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1731622 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   1827622 ps: (spi_device_ram_cfg_vseq.sv:23) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === dst_ram_cfg (0x3f9050 [1111111001000001010000] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   1827622 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)