SRAM_CTRL/MAIN Simulation Results

Monday April 28 2025 20:29:11 UTC

GitHub Revision: 841f73f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	15.150s	1.355ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.830s	29.975us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.730s	11.594us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.270s	47.879us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.710s	32.390us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.040s	1.476ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.730s	11.594us	1	1	100.00
		sram_ctrl_csr_aliasing	1.710s	32.390us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.679m	27.658ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.564m	8.308ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	8.875m	77.905ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.022m	13.587ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	5.300m	7.046ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	14.048m	21.456ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	51.910s	53.273ms	1	1	100.00
V2	executable	sram_ctrl_executable	9.143m	36.781ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	21.050s	731.205us	1	1	100.00
		sram_ctrl_partial_access_b2b	2.673m	4.695ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.033m	4.486ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	41.290s	2.964ms	1	1	100.00
		sram_ctrl_throughput_w_readback	5.410s	6.129ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	1.598m	12.566ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.220s	1.356ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	57.419m	172.357ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	2.010s	14.730us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.810s	235.046us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.810s	235.046us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.830s	29.975us	1	1	100.00
		sram_ctrl_csr_rw	1.730s	11.594us	1	1	100.00
		sram_ctrl_csr_aliasing	1.710s	32.390us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.580s	112.653us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.830s	29.975us	1	1	100.00
		sram_ctrl_csr_rw	1.730s	11.594us	1	1	100.00
		sram_ctrl_csr_aliasing	1.710s	32.390us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.580s	112.653us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	30.640s	7.848ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.620s	4.011us	0	1	0.00
		sram_ctrl_tl_intg_err	2.960s	410.288us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.620s	4.011us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.960s	410.288us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	1.598m	12.566ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	1.598m	12.566ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.730s	11.594us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	9.143m	36.781ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	9.143m	36.781ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	9.143m	36.781ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	51.910s	53.273ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	5.230s	691.000us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	30.640s	7.848ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.170s	3.332ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	15.150s	1.355ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	15.150s	1.355ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	9.143m	36.781ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.620s	4.011us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	51.910s	53.273ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.620s	4.011us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.620s	4.011us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	15.150s	1.355ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.620s	4.011us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	8.020s	316.839us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.14674145966750600591797988168742531635252260056919165107824971034311467262020
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   4010714 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   4010714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---